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Michael Schaffner msfschaffner @google @GoogleCloudPlatform USA

PrincetonUniversity/openpiton 251

The OpenPiton Platform

pulp-platform/pulpissimo 132

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

pulp-platform/ntx 2

A floating-point streaming accelerator.

msfschaffner/ariane 1

Ariane is a 6-stage RISC-V CPU

msfschaffner/edalize 1

An abstraction library for interfacing EDA tools

msfschaffner/fusesoc 1

Package manager and build abstraction tool for FPGA/ASIC development

msfschaffner/ibex 1

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

msfschaffner/openpiton 1

The OpenPiton Platform

msfschaffner/opentitan 1

OpenTitan: Open source silicon root of trust

msfschaffner/style-guides 1

lowRISC Style Guides

pull request commentlowRISC/opentitan

[usbdev] Fixes for pin config sims to pass

Thanks for restoring the pinflip/mode simulation! The HW changes look fine (sorry for breaking flipped operation).

I agree with your comment regarding disabling se0/reset detection during TX. It's probably fine in most PHY implementations, but it seems like a good idea anyway.

mdhayter

comment created time in 20 minutes

Pull request review commentlowRISC/opentitan

[DV] Updates to the way SW is built for DV simulations

+// Copyright lowRISC contributors.+// Licensed under the Apache License, Version 2.0, see LICENSE for details.+// SPDX-License-Identifier: Apache-2.0++package str_utils_pkg;+  `include "dv_macros.svh"++  // Helper function to see if string 's' has substring 'sub'+  function automatic bit str_has_substr(string s, string sub);+    for (int i = 0; i < (s.len() - sub.len() + 1); i++) begin+      if (s.substr(i, i + sub.len() - 1) == sub) begin+        return 1;+      end+    end+    return 0;+  endfunction : str_has_substr++  // Returns the index of first occurrence of string 'sub' within string 's'+  // If 'sub' does not occur within 's', returns -1.+  function automatic int str_find(string s, string sub);+    for (int i = 0; i < (s.len() - sub.len() + 1); i++) begin+      if (s.substr(i, i + sub.len() - 1) == sub) begin+        return i;+      end+    end+    return -1;+  endfunction : str_find++  // Returns the index of last occurrence of string 'sub' within string 's'+  // If 'sub' does not occur within 's', returns -1.+  function automatic int str_rfind(string s, string sub);+    for (int i = (s.len() - sub.len()); i >= 0; i--) begin+      if (s.substr(i, i + sub.len() - 1) == sub) begin+        return i;+      end+    end+    return -1;+  endfunction : str_rfind++  // This function strips all whitespace and any errant newline characters+  // from the LHS and RHS of the input string.+  // Assumes that the input string has non-zero length.+  //+  // TODO: Only single characters supported.+  function automatic string str_strip(string s,+                                      string chars[$] = {" ", "\n", "\t", "\r"},+                                      bit lstrip = 1'b1,+                                      bit rstrip = 1'b1);++    // Clean LHS+    if (lstrip) begin+      while (s.getc(0) inside {chars}) begin+        s = s.substr(1, s.len() - 1);+      end+    end++    // Clean RHS+    if (rstrip) begin+      while (s.getc(s.len() - 1) inside {chars}) begin+        s = s.substr(0, s.len() - 2);+      end+    end+    return s;+  endfunction : str_strip++  // This function splits the input `string` on the given delimiter `delim`, strips each substring+  // using `str_strip(...)`, and pushes them into the `result` queue.+  //+  // TODO: allow arbitrary length delimiter.

Ah, that works. My point was that stripping based on the delimiter looks a little odd (for example, if the delimiter is "AB", how would split+strip work with "aABABc": would it give ["a", "c"] or ["a", "", "c"]?). But, yep, if we're just stripping spaces then it looks good to me.

sriyerg

comment created time in 30 minutes

issue commentlowRISC/opentitan

[dvsim] Allow multiple `en_build_mode` values for a single test

Sounds like a good idea. I guess the challenge is working out how to avoid having to change all the other configs to use singleton lists. Maybe we could teach the "mode merging" code to allow either option?

udinator

comment created time in 33 minutes

Pull request review commentlowRISC/opentitan

[otbn] Update spec to allow mulqacc to set flags

     - *mulqacc-wrs2     - *mulqacc-wrs2-qwsel     - *mulqacc-acc-shift-imm+    - *bn-flag-group-operand   syntax: |     [<zero_acc>] <wrd>.<wrd_hwsel>,-    <wrs1>.<wrs1_qwsel>, <wrs2>.<wrs2_qwsel>, <acc_shift_imm>+    <wrs1>.<wrs1_qwsel>, <wrs2>.<wrs2_qwsel>, <acc_shift_imm>[, FG<flag_group>]   glued-ops: true   doc: |-    Multiplies two `WLEN/4` WDR values, shifts the product by `<acc_shift_imm>` and adds the result to the accumulator.-    Next, shifts the resulting accumulator right by half a word.-    The bits that are shifted out are written to a half-word of `<wrd>`, selected with `<wrd_hwsel>`.-+    Multiplies two `WLEN/4` WDR values, shifts the product by `acc_shift_imm` bits and adds the result to the accumulator.+    Next, shifts the resulting accumulator right by half a word (128 bits).+    The bits that are shifted out are written to a half-word of `wrd`, selected with `wrd_hwsel`.++    This instruction has slightly complicated rules for how it updates the flags in `flag_group`.

Good point. I probably wrote that sentence after drafting the stuff that followed for the third time :-)

rswarbrick

comment created time in 38 minutes

push eventlowRISC/opentitan

Rupert Swarbrick

commit sha 0789ce427880ad60948ae8aae6769623fd515583

[otbn] Fix circular dependency in gen-binaries.py Intriguingly, if you just run "ninja" on the result (without specifying smoke.elf as the target), it silently skips the rule. Huh?! Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

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PR merged lowRISC/opentitan

Reviewers
[otbn] Fix circular dependency in gen-binaries.py Component:OTBN Component:Tooling Type:Bug

Intriguingly, if you just run "ninja" on the result (without specifying smoke.elf as the target), it silently skips the rule. Huh?!

+1 -1

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1 changed file

rswarbrick

pr closed time in 41 minutes

PR opened lowRISC/opentitan

Reviewers
[keymgr/dv] Update scoreboard

Connect keymgr_kmac_monitor to scb and add following checks

  1. Add adv data check
  2. Add kmac key check, sw_share_output check
  3. Add WORKING_STATE, OP_STATUS check

minor update in base_seq to reduce redundency

+397 -28

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6 changed files

pr created time in 2 hours

PR opened lowRISC/opentitan

Reviewers
[otp/dv] support secret digest check

This PR support secret digest value check in scb. Different from normal digest, secret digest's input data is not direct write data. It needs to go through a scramble algo. The challenge here is when we use backdoor, the data is already scrmabled by OTP. So we need to descramble it to ensure the consistency in scb.

Signed-off-by: Cindy Chen chencindy@google.com

+123 -25

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3 changed files

pr created time in 5 hours

pull request commentlowRISC/opentitan

[usbdev] Fixes for pin config sims to pass

@vogelpi @stefanlippuner Can you take a look? I have not tried FPGA yet but this gets all combinations of pin flip and differential working again in simulation.

One issue with the move of reset detection to the usbdev_linkstate is it depends on the PHY reflecting the line state (or anything other than SE0) on the rx dp/dn when it is driving. My DPI had it sending SE0 (because that is what the single ended tx signals were in differential mode) so it detected reset during any long enough transmission. This is probably a fine assumption although I am tempted to pull the tx enable into linkstate and use it to qualify SE0 detection just so the main logic is robust against different PHY implementations.

mdhayter

comment created time in 6 hours

PR opened lowRISC/opentitan

[usbdev] Fixes for pin config sims to pass

Fix issues simulating usbdev with script in top_earlgrey/util

  • Bug introduced in latest iomux changes in single-end flipping

  • usbdpi fake phy not reflecting true line state when device driving This caused the rx to see SE0 when in differential mode thus reset

  • Final !!! output has moved because program timing changes If the code misses push at frame 0x11 it skips to 0x21

  • Line number changes in expected output

  • Expected output renamed without .log to avoid gitignore

Signed-off-by: Mark Hayter mark.hayter@gmail.com

+155 -10

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6 changed files

pr created time in 6 hours

push eventlowRISC/opentitan

Cindy Chen

commit sha 98b1136161605aae86e55bd21efc58bc38f3ccd5

[dv/otp_ctrl] fix mem_walk uvm_not_ok error In test_access mem_walk automation sequence, there are regression errors saying UVM_STATUS is not okay. This is because the testbench trying to read/write test_access memory the same cycle as `lc_dft_en` is set to `ON`. However, the `lc_dft_en` needs one clock cycle to update the FSM state register. So the fix here adds some delay after drive `lc_dft_en` pin. Signed-off-by: Cindy Chen <chencindy@google.com>

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PR merged lowRISC/opentitan

Reviewers
[dv/otp_ctrl] fix mem_walk uvm_not_ok error

In test_access mem_walk automation sequence, there are regression errors saying UVM_STATUS is not okay.

This is because the testbench trying to read/write test_access memory the same cycle as lc_dft_en is set to ON. However, the lc_dft_en needs one clock cycle to update the FSM state register.

So the fix here adds some delay after drive lc_dft_en pin.

Signed-off-by: Cindy Chen chencindy@google.com

+2 -0

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1 changed file

cindychip

pr closed time in 7 hours

pull request commentlowRISC/opentitan

[top_earlgrey/rtl] adding csrng and edn blocks

@eunchan @msfschaffner can you check the inter signal connections between csrng and edn. I was unable to connect more than one port of the csrng app interface because the DV ENV does not appear to support multiple reg instances of a module, at least out of the box. Because of this, lots of TODOs were left until support is available. @sriyerg can you confirm that my observation is correct, and what the fix might be.

If it's just internal signal increased, I feel DV ENV should support it. Let me try this out.

one failure is because we don't support generate RAL reg package for a IP with multiple instances in the top. Let me see if I can quickly add that support.

just created $4309 to address this. I uncommented those TODOs in my local and Smoke is passing with that fix

mwbranstad

comment created time in 7 hours

PR opened lowRISC/opentitan

[dv/common] Update ral generation to support IP with multi-instance

First commit is just to fix style error by running lintpy. can skip reviewing it Send commit is to address #4211 and #2482

+69 -68

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3 changed files

pr created time in 7 hours

Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 def create_regressions(regdicts, sim_cfg, tests):                 if sim_mode_obj.name in sim_cfg.en_build_modes:                     continue -                # Merge the build and run opts from the sim modes+                # Merge the build and run cmds & opts from the sim modes+                regression_obj.pre_build_cmds.extend(+                    sim_mode_obj.pre_build_cmds)+                regression_obj.post_build_cmds.extend(+                    sim_mode_obj.post_build_cmds)                 regression_obj.build_opts.extend(sim_mode_obj.build_opts)+                regression_obj.pre_run_cmds.extend(sim_mode_obj.pre_run_cmds)+                regression_obj.post_run_cmds.extend(sim_mode_obj.post_run_cmds)                 regression_obj.run_opts.extend(sim_mode_obj.run_opts)

I am scared to say yes, after looking at the monstrosity in #3779 :-D

I'd prefer to document it and take the "don't fix if it ain't broke" approach. We can address it after tape-out. Right now, there are more pressing matters at hand.

sriyerg

comment created time in 7 hours

Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 def construct_cmd(self):                 pretty_value = []                 for item in value:                     pretty_value.append(item.strip())-                value = " ".join(pretty_value)+                # Join attributes that are list of commands with '&&' to chain+                # them together when executed as a Make target's recipe.+                if attr in self.cmds_list_vars:+                    value = " && ".join(pretty_value)+                else:+                    value = " ".join(pretty_value)

Done.

sriyerg

comment created time in 8 hours

Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 prep_tool_srcs: 	${LOCK_TOOL_SRCS_DIR} "cp -Ru ${tool_srcs} ${tool_srcs_dir}/."  pre_compile: prep_tool_srcs-	@echo "[make]: pre_compile"+	@echo "[make]: pre_build" 	mkdir -p ${build_dir}+ifneq (${pre_build_cmds},)+	cd ${build_dir} && ${pre_build_cmds}+endif

This will require adding intelligence in DVSim to not set pre_build_cmds="" et al if they are not is supplied in the HJson, so that the empty string does not override the default true. I think I prefer keeping this instead.

sriyerg

comment created time in 8 hours

Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 def __init__(self, sim_cfg):             "dry_run": False         } +        # List of variable names that are to be treated as "list of commands".+        # This tells `construct_cmd` that these vars are lists that need to+        # be joined with '&&' instead of a space.+        self.cmds_list_vars = []

Ok, done.

sriyerg

comment created time in 8 hours

Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 name:   // TODO: This needs deciding upon. Eventually, it might be nice to allow this   //       to be overridden on the command line ("I've got a bunch of ELF files   //       that stress my new feature; please run the test suite with them")-  otbn_elf_dir: "{sw_build_dir}"-+  otbn_elf_dir: "{run_dir}/build-out"   run_opts: ["+otbn_elf_dir={otbn_elf_dir}"] +  // OTBN run modes.+  run_modes: [+    {+      name: build_otbn_rig_binaries_mode+      pre_run_cmds: ["BUILD_ROOT={run_dir} cd {proj_root} && ./meson_init.sh",+                     "{proj_root}/hw/ip/otbn/dv/uvm/gen-binaries.py --seed {seed} {otbn_elf_dir}"]

Yes we do. I prefer to avoid making any assumptions such as things that should have been run before kicking off a sim. All chip level tests (which compile and generate all required SW images for the test as a pre-run step within DVSim) are fully contained, in that no extra steps are needed before running any of the tests. This is why we added a good deal of capability into it.

sriyerg

comment created time in 10 hours

pull request commentlowRISC/opentitan

Improvements to how dvsim.py runs jobs

Another week, another rebase. No intentional changes, although I did have to spend some time fixing things up when rebasing past recent dvsim changes. It's a bit of a pity that this is gently bit-rotting.

It indeed is unfortunate. It has been already communicated that non-urgent / non-bug-fix enhancements like these, especially when its a mishmash of commits that make changes to several different parts of the code, will be reviewed with a much lower priority. There are at least 4 discrete meaningful changes in here that could have been submitted as separate PRs, which would have been a lot easier / smoother to review. Separate commits in the same PR is not at all helpful, if the diff in latter commits is against your own code from previous commits!

I have already communicated before - large, non-urgent PRs will be looked at with a lower priority (expect an SLO of ~60 days). If that is unacceptable, please justify. If it is urgent, please file an issue so that the priority is understood.

@domrizz0 @asb @sjgitty @tomroberts-lowrisc

rswarbrick

comment created time in 7 hours

issue commentlowRISC/opentitan

[otbn] Evaluate the removal of START_ADDR

Ibex is still trusted to load code on OTBN, so TCB wise no changes here.

If all the PKA functions don't fit into IMEM, I assume we can break them down into separate programs.

@imphil I have a few follow up questions to try to parse the proposal in more detail:

  • What would replace START_ADDR? I expect Ibex to be able to start OTBN execution with an expected deadline.
  • From a perturbation perspective, we can claim we are mitigating a glitch point by removing START_ADDR, but we are adding new potential points in the new branching code. What are the tradeoffs from a FI perspective?
  • Moreover, by adding additional compare/branches you are claiming that it is easier to statically analyze the assembly, why isn't this the same as just tagging the API, and have each entry function handle the control flow state initialization?
imphil

comment created time in 8 hours

pull request commentlowRISC/opentitan

[top_earlgrey/rtl] adding csrng and edn blocks

@eunchan @msfschaffner can you check the inter signal connections between csrng and edn. I was unable to connect more than one port of the csrng app interface because the DV ENV does not appear to support multiple reg instances of a module, at least out of the box. Because of this, lots of TODOs were left until support is available. @sriyerg can you confirm that my observation is correct, and what the fix might be.

If it's just internal signal increased, I feel DV ENV should support it. Let me try this out.

one failure is because we don't support generate RAL reg package for a IP with multiple instances in the top. Let me see if I can quickly add that support.

mwbranstad

comment created time in 8 hours

issue openedlowRISC/opentitan

[dvsim] Add support for running arbitrary commands before / after builds and runs

This is needed to support OTBN, which requires some binaries to be built before launching a simulation run.

created time in 9 hours

pull request commentlowRISC/opentitan

[DV] Updates to the way SW is built for DV simulations

Fixes #4307.

sriyerg

comment created time in 9 hours

issue openedlowRISC/opentitan

[dvsim] Add support for building an arbitrary list of SW images

This is required for the chip level, which currently assumes only one boot rom image and one SW test image to be built for a test. This need to be made a bit more robust as support for OTBN and other updates to the SW architecture come in future.

created time in 9 hours

pull request commentlowRISC/opentitan

[kmac/dv] Add new sim_cfg and testplan Hjson files

@weicaiyang I think i have a workaround for this, I can override the scratch_base_path variable in each of the kmac_masked and kmac_unmasked config files, wdyt? Not sure if this could be too intrusive of an override. I'll push this modification so you can see what I mean.

Great. LGTM

udinator

comment created time in 9 hours

pull request commentlowRISC/opentitan

[kmac/dv] Add new sim_cfg and testplan Hjson files

@weicaiyang I think i have a workaround for this, I can override the scratch_base_path variable in each of the kmac_masked and kmac_unmasked config files, wdyt? I'll push this modification so you can see what I mean.

udinator

comment created time in 9 hours

pull request commentlowRISC/opentitan

[kmac/dv] Add new sim_cfg and testplan Hjson files

will simulations output into the same directory since both are in {dut}.sim.{tool}

hmm that is a good point actually. Will try changing each DUT variant's {dut} name to resolve this.

I assume {dut} is the module name of the dut in UNR, in this case, it must be kmac. perhaps changing dvsim to output to {name}.sim.{tool} is better, or find a way to override this output directory. @sriyerg any thoughts?

yes, changing the {dut} might mess with some other flows using dvsim. I pushed the modified names just as a reference here to see how it would look, but like you said maybe some way of overriding the output directory would be a much better solution.

udinator

comment created time in 9 hours

pull request commentlowRISC/opentitan

[kmac/dv] Add new sim_cfg and testplan Hjson files

will simulations output into the same directory since both are in {dut}.sim.{tool}

hmm that is a good point actually. Will try changing each DUT variant's {dut} name to resolve this.

I assume {dut} is the module name of the dut in UNR, in this case, it must be kmac. perhaps output to {name}.sim.{tool} is better, or find a way to override this output directory. @sriyerg any thoughts?

udinator

comment created time in 9 hours

pull request commentlowRISC/opentitan

[kmac/dv] Add new sim_cfg and testplan Hjson files

will simulations output into the same directory since both are in {dut}.sim.{tool}

hmm that is a good point actually. Will try changing each DUT variant's {dut} name to resolve this.

udinator

comment created time in 9 hours

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