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Greg Chadwick GregAC Cambridge, UK

GregAC/rpi-v3d 1

A collection of tools and libraries for working with V3D on the Raspberry Pi

lowRISC/gsoc-sim-mem 1

A simulated memory controller for use in FPGA designs that want to model real system performance

GregAC/edalize 0

An abstraction library for interfacing EDA tools

GregAC/embench-iot 0

The main Embench repository

GregAC/ibex 0

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

GregAC/opentitan 0

OpenTitan: Open source silicon root of trust

GregAC/riscv-dv 0

SV/UVM based instruction generator for RISC-V processor verification

GregAC/style-guides 0

lowRISC Style Guides

issue openedlowRISC/opentitan

Newbie guide to contributing fixes to Opentitan

Hello, One question while I was trying to fix some low hanging issues on Riviera/Questa support.

From https://github.com/lowRISC/opentitan/blob/master/CONTRIBUTING.md I read:

Create pull requests from a fork rather than making new branches in github.com/lowrisc/opentitan.

I generally follow the fork --> clone --> add remote --> branch --> commit flow as in:

https://jarv.is/notes/how-to-pull-request-fork-github/

Do you folks differ slightly in that, you don't want me to create a branch?

Also, what exactly you mean by "do not commit" - how do I raise a pull request otherwise?

Sorry if this is too simple, but not so obvious to me.

Regards Srini

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Rupert Swarbrick

commit sha 690f8af65ec1b355f7283f8f5f6961810a650bca

Update paths for vendored DV code This commit amends some paths in the vendoring hjson file (and updates config files to use things at the new paths). Finally it re-runs the vendoring tool: Update code from upstream repository https://github.com/lowRISC/opentitan to revision 92e9242424c72c59008e267dd3779e2af5ec8e83 which just ends up with a load of file renames. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

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Rupert Swarbrick

commit sha 623402cf6fa4534eea71c297b83f3c742f5db662

Vendor in hw/dv/{data,tools} from OpenTitan This gets the rest of the support code needed for dvsim (which we currently duplicate). The patch: - adds the relevant directories to the vendoring file - adds a patch to rewrite some OpenTitan-specific bits - adds a "common_project_cfg.hjson" - re-runs the vendoring tool This patch won't yet change how DV code runs; we also need to redirect a couple of paths and delete dv/uvm/data for that. This will happen in the next patch. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

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Rupert Swarbrick

commit sha 3d8041597b0bb4225e13a43a0bb3f48dfd40831b

Delete dv/uvm/data and point DV code at the vendored version This teaches the DV environment to use the vendored code that we set up in the previous patch.

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Rupert Swarbrick

commit sha 31a18ad10c91f41c2abb27746683812656f1d566

Clear MAKEFLAGS when running dvsim.py dvsim.py runs make as a subprocess, which gets rather confused if MAKEFLAGS appears in its environment. The proper fix is to clear them from the environment in the dvsim command: we'll do that on the OpenTitan side[1] and can revert this patch once that change is vendored in. [1] https://github.com/lowRISC/opentitan/pull/4325

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Rupert Swarbrick

commit sha 4852e307b7f6112ea763da2b072a64099b82d994

Update lowrisc_ip to lowRISC/opentitan@e619fc60 This updates the vendored code from OpenTitan and fixes up patches as we go. The biggest change is that the support files that were in dv/data have moved to dv/tools/dvsim (with a couple of other internal renames). The icache test code also needs the corresponding path change and to rename its regression from "sanity" to "smoke" (the new name for the default regression). Update code from upstream repository https://github.com/lowRISC/opentitan to revision e619fc60c6b9c755043eba65a41dc47815612834 * [dv] Remove duplicated keys from common_sim_cfg.hjson (Rupert Swarbrick) * [dv] two small fix in dv (Cindy Chen) * [dv] Comment out example build modes from common_sim_cfg.hjson (Rupert Swarbrick) * [dv/keymgr] Cleanup some warnings in xcelium (Weicai Yang) * [lc_ctrl] Reuse an instance of the RISC-V dmi_jtag as the LC TAP (Michael Schaffner) * [otp_ctrl] Update LC types within OTP (Michael Schaffner) * [lc_ctrl] Add first cut implementation (Michael Schaffner) * [flash_ctrl] update prim flash interface (Timothy Chen) * [flash_ctrl] Add support for isolated flash partition (Timothy Chen) * [dv/common] update naming from sanity to smoke (Cindy Chen) * [prim] update naming from sanity to smoke (Cindy Chen) * [dv/base] add get_reg_by_name support in dv_base_reg_block (Cindy Chen) * [cov methodology] Functional coverage prototype (Srikrishna Iyer) * [dv] Fix tpyo (Weicai Yang) * [dv common] Wave dumping improvements / fix (Srikrishna Iyer) * [dv] Fix for `--run-only` switch (Srikrishna Iyer) * [prim_present] Add support for iterative full-round PRESENT (Michael Schaffner) * [dv] Fix VCS compile error (Weicai Yang) * [sparse-fsm-encode] Switch to Safe Rust Encoding (Sam Elliott) * [sparse-fsm-encode] Disallow Complementary Encodings (Sam Elliott) * [prim/util] Fix parameter type when using prefixes (Pirmin Vogel) * [keymgr/prim_lfsr] Correct minor errors in core files (Michael Schaffner) * [design checklist] avoid using word sanity (Cindy Chen) * [prim_lc_sync] Add two stage sync for life cycle control signals (Michael Schaffner) * [flash] update flash program to support ack / done / last (Timothy Chen) * [prim] update prim flash to have ack / done support (Timothy Chen) * Fix typo in testplan template (Rupert Swarbrick) * [dv] Fix license header for some cfg files (Weicai Yang) * [dv] Only check scoreboard from pre_abort if we were in run phase (Rupert Swarbrick) * [doc] Add lint requirements to V1 checklist (Cindy Chen) * [dv common] Minor enhancements to dv_reg_block (Srikrishna Iyer) * [dv] Fix library paths for dsim (Srikrishna Iyer) * [keymgr/dv] Update testbench (Weicai Yang) * [dv/common] Add DV_ALERT_IF_CONNECT macro (Weicai Yang) * [dv, common] Promote VCS warning to error (Srikrishna Iyer) * [prim] update clock_mux prim to avoid using BUFG (Timothy Chen) * [clkmgr] Add divider bypass during test mode (Timothy Chen) * [opt_ctrl] Change state_q assignment to ease debugging (Michael Schaffner) * [doc] Update D2 checklist and propagate updates to IPs (Michael Schaffner) * [dv/dvsim] Fix -c option compile error (Cindy Chen) * [dv] Tidy up use of get_normalized_addr (Rupert Swarbrick) * [fpv] Fix fusesoc dependecy issue (Cindy Chen) * [lint] Fix lint warning (Cindy Chen) * [dv/lint] Add new DV TB to lint batch script (Cindy Chen) * [fpv] Add lint checking to FPV tb (Cindy Chen) * [dvsim] Remove process_exports() from the code (Srikrishna Iyer) * [dvsim] Fix HJson bugs (Srikrishna Iyer) * [fpv] alert_rx/tx updates (Cindy Chen) * [prim] slicer lint fix (Eunchan Kim) * [prim] Packer to remove unused parameter. (Eunchan Kim) * [prim_lfsr] Update prim_lfsr and testbench to use correct perm width (Michael Schaffner) * [prim_lfsr] Add script to generate seed and perm constants (Michael Schaffner) * [dv/common] Upgrade some VCS warnings to errors (Weicai Yang) * [dvsim] Document and slightly improve subst_wildcards in utils.py (Rupert Swarbrick) * [csrng/dv] Initial dv environment (Steve Nelson) * [sparse-fsm-encode] Update template to prevent JG compile error (Michael Schaffner) * Gracefully shut down Verilator when software test fails (Philipp Wagner) * [otp] fix FPV compile error (Cindy Chen) * [dvsim] Kill subprocesses more gracefully (Rupert Swarbrick) * [prim] Fix Verilator lint warnings (Pirmin Vogel) * [memutil] Allocate the right number of bytes in StagedMem::GetFlat() (Rupert Swarbrick) * [memutil] Load ELF files via a staging area (Rupert Swarbrick) * [memutil] Add iterator and merging insertion interfaces to RangedMap (Rupert Swarbrick) * [memutil] Factor out "ranged map" implementation from dpi_memutil (Rupert Swarbrick) * [alert_handler] update alert hander ports (Timothy Chen) * [otp_ctrl] Update OTP output data mapping (Michael Schaffner) * [otp_ctrl] Split partition metadata into separate package (Michael Schaffner) * [prim_otp] Add TL-UL regfile for testing (sim only) (Michael Schaffner) * [memutil] Split out the non-verilator part of verilator_memutil (Rupert Swarbrick) * [dv/common] Update DV_CHECK_* macros (Weicai Yang) * [dv/common] Fix testplan path (Weicai Yang) * [prim_assert] Fixed non-UVM part of `ASSERT_ERROR (Srikrishna Iyer) * [otp_ctrl] Simplify and consolidate OTP error codes (Michael Schaffner) * [kmac] Fix critical syntax errors. (Eunchan Kim) * [dv/common] Move testplan from tools directory to data (Weicai Yang) * [dvsim] Rename verbosity wildcards to something more informative (Rupert Swarbrick) * [dv/lfsr] Update prim_lfsr_sim_cfg.hjson and add coverage (Udi Jonnalagadda) * [dv common] Added string check macros (Srikrishna Iyer) * [rtl] Use platform-agnostic log macros prim_assert (Srikrishna Iyer) * [dv] Minor fixups to dv_Utils_pkg (Srikrishna Iyer) * [dv] Fix platform-agnostic log macros (Srikrishna Iyer) * [checklist] Upgrade wording for D1 milestone (Scott Johnson) * [entropy_src/rtl] fix for dv sanity test (Mark Branstad) * [lint] Add option to bail out on first invalid Tcl cmd (Michael Schaffner) * [sram_ctrl] Add first cut implementation (Michael Schaffner) * [prim] Fix AscentLint waiver that made the tool crash (Michael Schaffner) * [checklists] Clean up and align HW and SW checklists (Michael Schaffner) * [prim] Update signal name in lint waiver rule (Pirmin Vogel) * [flash_ctrl] Switch to new keyschedule in PRINCE (Michael Schaffner) * [lint] fix the waiver format (Eunchan Kim) * [dv] Waive lint warnings in dv_macros.svh (Srikrishna Iyer) * [dv common] Add platform-agnostic log macros (Srikrishna Iyer) * [util] Add Rust Enum Support to sparse-fsm-encode.py (Sam Elliott) * [util] Add C Enum Support to sparse-fsm-encode.py (Sam Elliott) * [sparse-fsm-encode] Expand error and help messages (Michael Schaffner) * [dv/common] TLUL agent function coverage (Weicai Yang) * [dv/shadow_reg] support alert handshake checking (Cindy Chen) * [prim_present/otp_ctrl] Add round index state IOs to primitive (Michael Schaffner) * [dv] Fix 2 regression failures (Weicai Yang) * [prim_multibit_sync] Add multibit synchronizer with consistency check (Michael Schaffner) * [prim] Fix Lint warning for prim_slicer (Eunchan Kim) * [prim_generic_otp] Add TL-UL test interface stub for DV (Michael Schaffner) * [doc] Improve documentation for common_ifs (Rupert Swarbrick) * [doc] Improve pins_if block diagram (Rupert Swarbrick) * [prim_prince/present] Remove TODOs (Michael Schaffner) * [dv/common] Change TL item content when it's not accepted (Weicai Yang) * [dv/uvmgen] update has_alerts (Cindy Chen) * [dv/common] Add run opt plusarg to enable file path in the log (Weicai Yang) * [prim] Add clock buffer primitive for Xilinx FPGAs (Pirmin Vogel) * [otp_ctrl] Provision power sequencing signals (Michael Schaffner) * [dv/common] Clean up old makefile flow (Weicai Yang) * [entropy_src/rtl] review round2 changes (Mark Branstad) * [otp_ctrl] Update all FSMs to use prim_flop for the state (Michael Schaffner) * [prim_xilinx_flop] Add a Xilinx version with keep attribute (Michael Schaffner) * [prim/util] Update sparse-fsm-encode and include FSM template (Michael Schaffner) * [DV macros] minor enhancement to `DV_SPINWAIT (Srikrishna Iyer) * [DV common] Add DV_ASSERT_CTRL macro (Srikrishna Iyer) * [DV common] Enhance `DV_CHECK_MEMBER_RANDOMIZE_*` (Srikrishna Iyer) * [otbn] Use relative scope names for OTBN scopes (Rupert Swarbrick) * [verilator simutil] Add support for relative scope names to SVScoped (Rupert Swarbrick) * [fpv/prim_packer] remove assumption (Cindy Chen) * [fpv/csr_assert] support all modules for CSR assert (Cindy Chen) * [memutil] Teach verilator_memutil to load multi-segment ELF files (Rupert Swarbrick) * [memutil] Simplify how we read ELF files in verilator_memutil.cc (Rupert Swarbrick) * [memutil] Add a "verbose" flag to detail memory loads (Rupert Swarbrick) * [memutil] Parse all arguments before loading anything (Rupert Swarbrick) * [memutil] Use override keyword, not virtual for overridden method (Rupert Swarbrick) * [memutil] Use exceptions to simplify error handling (Rupert Swarbrick) * [memutil] Store the width of memory areas in bytes, not bits (Rupert Swarbrick) * [memutil] Allow memory locations to have associated LMAs (Rupert Swarbrick) * [memutil] Improve type of ElfFileToBinary in verilator_memutil.cc (Rupert Swarbrick) * [verilator simutil] Move SVScoped class into dv/verilator/cpp (Rupert Swarbrick) * [memutil] Move static functions out of VerilatorMemUtil class (Rupert Swarbrick) * [memutil] Run clang-format on verilator_memutil.* (Rupert Swarbrick) * [dv:entropy_src] Initial rng_agent and integrated into entropy_src env (Steve Nelson) * [prim_ram_adv/fpv] fix assertion (Cindy Chen) * [prim_ram_1p_scr] Simplify nonce input and align to multiples of 64b (Michael Schaffner) * [fpv/csr_assert] add csr support for regwen (Cindy Chen) * [prim*] Various lint fixes in the prims (Michael Schaffner) * [prim] remove FPV related assertions (Eunchan Kim) * [prim_lfsr] Add option to supply custom output permutation (Michael Schaffner) * [dv/common] calculate addr map size in RAL (Weicai Yang) * [flash_ctrl] Add ECC to program / erase datapaths (Timothy Chen) * [otp_ctrl] First cut implementation of the OTP controller (Michael Schaffner) * Fix invalid read in verilator_memutil (Rupert Swarbrick) * [doc] Don't strip markdown headings from HW checklist (Philipp Wagner) * [site] Set lint title (Tobias Wölfel) * [dv/prim] add basic PRINCE testbench (Udi Jonnalagadda) * [flash_ctrl] Support the notion of a 'program-repair'. (Timothy Chen) * [prim/tlul] Various small lint fixes (Michael Schaffner) * [dv/uvmdvgen] update dvsim and remove Makefile (Cindy Chen) * [util] Add script for generating sparse FSM encodings (Michael Schaffner) * [prim] Add option to register output for interrupts (Timothy Chen) * [prim_otp] First cut implementation of FPGA emulation (Michael Schaffner) * [prim_ram_1p_adv] Add 16bit ECC mode (Michael Schaffner) * [chip dv] Fix for failing GPIO test (Srikrishna Iyer) * [RTl] Generic pad wrapper default behavior fix (Srikrishna Iyer) * [slicer] Select partial from bitstream (Eunchan Kim) * [util] Don't hack __repr__ in FlowCfg (Rupert Swarbrick) * [util] Fix lint in dvsim.py (Rupert Swarbrick) * [fpv/prim_packer] Add a FPV TB (Cindy Chen) * [Keccak] Keccak_f implementation (Eunchan Kim) * [dv/csr] add common task for csr_or_field_rd_check (Cindy Chen) * [keccak] Add valid signal to random value (Eunchan Kim) * [prim] Add primitive clock divider (Timothy Chen) * [dv/shadow_reg] update sequence for storage error (Cindy Chen) * [dv/lib] clear csr_outstanding_access after reset (Cindy Chen) * [sw] Ensure Headers are Correctly Ordered (Sam Elliott) * [dv] Fix csr_rd check during reset (Weicai Yang) * Adding the first update to coverage methodology (Rasmus Madsen) * [dv] TL agent supports no clock reset (Weicai Yang) * [tlul/dv] Update test plan for tl errors (Weicai Yang) * [fpv/alert] update namings for FPV tb (Cindy Chen) * [keccak] Masked/Unmasked Keccak single round (Eunchan Kim) * [lint/prim*] Waive STAR_PORT_CONN_USE errors in generated prims (Michael Schaffner) * [prim_usb_diff_rx] Carry over wrapper for USB diff receiver (Michael Schaffner) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

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Rupert Swarbrick

commit sha 4735a2684c47ec5090fdc467d43595075a0d7857

Avoid use of the term "sanity test" in icache UVM testbench

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PR merged lowRISC/ibex

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Vendor in the contents of dv/uvm/data and update to latest OpenTitan

This checks another box on issue #985 and (the reason I need this patch) gets the dvsim+VCS flow working with recent GCCs.

+9807 -3055

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rswarbrick

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pull request commentlowRISC/opentitan

[usbdev] Test on NexysVideo with TUSB1106 USB PHY PMOD

@vogelpi and @stefanlippuner need your thoughts on if we want this in the repo or I should just carry as a local change since I only made 3 of the special PMOD boards (I have parts for 3 more).

Stefan may have something similar (although I believe his test PHY chip was from someone other than TI).

mdhayter

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PR opened lowRISC/opentitan

[usbdev] Test on NexysVideo with TUSB1106 USB PHY PMOD

Add support in nexys video top and pins for having a PMOD with TUSB1106 USB PHY in PMOD JC. This allows testing of the usbdev in FPGA using a PHY with the same interface ase contemplated on the first OpenTitan chip implementation. The PHY uses single ended TX signals but has the differential RX needed by USB spec (with the single ended RX being used to detect SE0). The PHY also privides the pullup on D+. Direction is set by an active low OE (i.e. inverted from the comportable active high oe).

Top level FPGA wrapper supports both PMOD options based on SW2 (i.e. GPIO2). SW2=0 uses the single ended resistor only PMOD in connector JB (same as before). SW2=1 uses the TUSB1106 PMOD in connector JC. The wrapper supports faking pinswap for both PMODs. The single ended PMOD must be run with single ended configuration. The TUSB1106 can be set to use either single ended or differential RX but only supports single ended TX. (There were not enough pins on the PMOD connector to support the switchable TUSB1105.)

Modified the hello_usbdev code to detect the TI phy from SW2 and prevent differential TX when it is used.

Added the kicad files for the PMOD board to the usbdev/pmod directory.

Tested on Nexys Video with both PMODs and confirmed Verilator tests still run correctly (with line number and printf changes).

Signed-off-by: Mark Hayter mark.hayter@gmail.com

+90142 -14

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PR closed lowRISC/opentitan

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[entropy_src/dv] Changed sanity to smoke

Signed-off-by: Steve Nelson steve.nelson@wdc.com

+20 -21

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senelson7

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Steve Nelson

commit sha 8d54c6c660939fdd17a8a16ad533ad11eb783288

[csrng/dv] push_pull_agent parameter .DataWidth->.HostDataWidth Signed-off-by: Steve Nelson <steve.nelson@wdc.com>

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PR merged lowRISC/opentitan

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[csrng/dv] push_pull_agent parameter .DataWidth->.HostDataWidth

Signed-off-by: Steve Nelson steve.nelson@wdc.com

+19 -14

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senelson7

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Steve Nelson

commit sha 78e90e32fddddbfa35d7ef1581452b587ddb3a5c

[edn/dv] csrng_agent is only genbits, not cmd Signed-off-by: Steve Nelson <steve.nelson@wdc.com>

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PR merged lowRISC/opentitan

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[edn/dv] csrng_agent is only genbits, not cmd

…IOs, not cmd

Signed-off-by: Steve Nelson steve.nelson@wdc.com

+43 -27

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senelson7

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pull request commentlowRISC/ibex

Fix Jump Latency for Configuration with BTALU

I think this is correct. The branch target ALU accelerates conditional branches, by computing the branch target and the branch condition in parallel. For unconditional branches, i.e. jumps it makes no difference.

ganoam

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PR opened lowRISC/opentitan

[top] Add support for further top levels

Note: this PR is based on #4294 which contains various fixes to topgen (skip the first 7 commits here).

This PR adds support for additional top levels. This is needed for supporting different FPGAs. On one hand, already the bronze design cannot be implemented on the NexysVideo board. As we move towards silver, we will have to switch the main design to a bigger FPGA but we want to keep supporting low cost boards like the NexysVideo for the community. On the side channel analysis (SCA) front, the situation is even worse: already today, several crypto IPs need to be removed and the flash size needs to be reduced to make the design with a single hardened accelerator fit the smaller FPGA.

Wtih this PR, additional top levels to top_earlgrey can be supported. For those new top-levels, only the hjson config and template files, some top-level core and SystemVerilog files are added under hw/top_... but the auto-generated sources and core files are not added to the repo. These files are automatically generated by FuseSoC at build time by calling topgen under the hood (via generator, similar to what we do with the tech primitives). To this end, FuseSoC needs to be called with a fileset_topgen flag and IPs specific to the top-level (alert handler, clkmgr, rstmgr etc.) have a dependency to this new generator if the flag is specified.

As an example, this PR adds a second top level called top_englishbreakfast that will be used for side channel analysis (basically replacing top_earlgrey_cw305). The generated bitstream has been tested successfully on the ChipWhisperer CW305 FPGA board.

There are currently two workarounds implemented in this PR:

  1. We have hardcoded references to top_earlgrey in the software sources and the SW build configuration. The PR thus contains a script to patch the sources produced by topgen. I will need help from SW folks to solve this properly.
  2. Currently, topgen is run twice by FuseSoC. From the first run, we just take the auto-generated register files and from the second run, we take everything else (some packages, top level). Doing everything in one shot is currently not possible as this results in either unresolved dependencies or cyclic dependencies in FuseSoC. One way out of this would be to allow unresolved dependencies in FuseSoC before the generators (topgen) are run. This is tracked upstream olofk/fusesoc#449.
+5266 -81

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Srikrishna Iyer

commit sha 53415ce28934586cd73fa14f0b31ba5f6b50c98e

[DV common] String utils package - A dedicated package that provides string manipulation utility functions. Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha f9b0874cfc5a9123a9dbd3baac2cf6adb346d82d

[dv common] Update dv_utils to use str_utils_pkg Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha a17f941a4f55df41c2a661562a78cab342539776

[dv sw_logger_if] Update to use str_utils_pkg Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha 360e34cc2abcf41545f7d157fc6eea8b7b1d18e0

[chip dv] Move sw build directory - This removes one extra hierarchy in the sw build area for chip dv Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha de5efa04db21f9e1de9b1b8961017c83ee9a5dce

[dvsim] Replace `sw_test` with `sw_images` This change is part 1/4 commit series that updates the way SW tests are build for chip level. For the chip level SW tests to pass, all 4 commits are needed. This change reduces dependency on DVSim to process how SW images for each tests are set and built. The goal is to be able to supply an arbitrary list of images to build, rather than assuming a fixes set (ROM and SW test). The need for this change arose from one more addition - OTBN that requires an image to be built. The processing is now handled by `sim.mk` and testbench code. All SW build steps (specific to DV) are integrated into meson. Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha 250a399da5f055914ae9d70f10c69da595d33277

[DV] Update how --rodata-sections switch works This change is part 2/4 commit series that updates the way SW tests are build for chip level. For the chip level SW tests to pass, all 4 commits are needed. - THis change updates how `--rodata-sections` switch on this tool works. - The above switch can be supplied multiple times on the command line - all supplied sections will get appended (expanded) into a single list. Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha d8929edef7e4339f9433c39f2a885d438c747e6f

[dv, meson] Integrate DV SW build steps into meson This change is part 3/4 commit series that updates the way SW tests are build for chip level. For the chip level SW tests to pass, all 4 commits are needed. This integrates the step that extracts the logs and rodata sections from the embedded SW elf into meson. This change is only enabled for 'sim_dv' device, so others should remain unaffected. Previously, this was done in DV simulation flow `hw/dv/tools/dvsim/sim.mk`. Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha 10763589923efbff6421daca120097f00cab7e27

[DV] Update the was SW is built for DV This change is part 4/4 commit series that updates the way SW tests are build for chip level. For the chip level SW tests to pass, all 4 commits are needed. This change updates the SV / testbench code to enable the following: - An arbitrary list of SW images can be supplied for each test in the HJson - Each entry in this list is of the format <path-to-sw-test>.<index>.<flags> - Index and flags are optional for the flow, but necessary for chip DV env. Index # indicates what SW image it pertains to: 0 - ROM, 1 - SW test, 2 - OTBN. - The goal is to make it scalable and flexible to any future need that may arise. - The flags can be used for enabling custom modifications (such as build something differently). - The full list of sw_images is passed to the UVM env which breaks it down and sets the images paths for each (ROM, SW test, OTBN etc). Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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PR merged lowRISC/opentitan

Reviewers
[DV] Updates to the way SW is built for DV simulations

This series of commits updates the way SW is built for DV. The motivation was to have a single SW build command do all the steps required to generate all the required outputs. This builds on top of @lenary's change that adds SPIFlash host build as a dependency to SW tests. It includes the extraction of RODATA and log metadata from the built images which are used in DV logging method.

Also, the way SW tests to be built are supplied to DVSim via the HJSon config file is updated - this approach now allows an arbitrary number of SW images to be built to be supplied to DVSim. It is the job of the simulation Makefile to understand how they are to be built. Now , only one variable needs to be set - sw_images which is a list with the following format: [path/to/foo/test:0:flag1, path/to/bar/test:1:flag1:flag2], where each entry is the path to the SW test to be built in meson, followed by index and flags. Index and flags are separated using ':' delimiter. They are both optional. The index is used by the testbench to know what type of SW image is it (0- ROM, 1- SW test, 2- OTBN etc). Flags are additional indicators that can be used to customize their behavior.

This approach reduces the need for hardcoding any logic within DVSim (or having DVSim understand what all the test variables mean). Simulation Makefile is considered 'user' data which can be replaced if needed for a DUT requiring a more customized flow.

The first 3 commits are slightly unrelated - they add a str_utils_pkg to provide some common string manipulation methods for DV, but they are eventually used in this PR.

Commit 5 removes sw_test_is_prebuilt as a 'known' test variable - only thing DVSim needs to know is a list of sw_images.

Commit 6 updates the RODATA/logs extraction script.

Commit 7 integrates the DV specific steps during the SW build into meson.

Commit 8 kind of puts it all together, updating the SV side of the testbench.

These changes are a precursor to building images for OTBN using the RIG with the meson flow.

+538 -169

3 comments

25 changed files

sriyerg

pr closed time in a day

PR opened lowRISC/opentitan

[rom_ext] Remove Signature Identifier

This was left over from https://github.com/lowRISC/opentitan/pull/3733#issuecomment-726928866.

There are three other changes:

  • One adds verbose logging to the generator script, which makes it easier to understand how layout is being performed when the manifest is changed.
  • One updates the manifest.md to use the format from #4305.
  • One updates the assembly which is used for the skeleton of the ROM_EXT in the elf images (which we plan to auto-generate at some point).
+74 -94

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7 changed files

pr created time in a day

issue commentlowRISC/opentitan

[otbn] Should we supply PC or other information on error?

Sounds like a good idea. Maybe we should just expose "stopping pc" on the register interface, updated with the current PC whenever OTBN stops. Since we don't have any exception handling, I think this will give what we want (and should be pretty trivial to plumb in).

There is a slight information leak, which might be a problem on the security side. For example, suppose that my code does some data dependent control flow from which I can extract secret information. Then I can fire alpha particles (or whatever!) at the chip during the run and read out the PC at my leisure. Maybe we just need to have an enable register that turns this feature on or off? Then the Ibex code can turn it on when doing on-silicon debug, and leave it turned off the rest of the time.

This question probably needs some security review.

@felixmiller: Do we have any code that does data-dependent branching? Will we?

@moidx, @cdgori: This looks like it would be helpful for debugging. Are there any other "security elephant traps" that we should be careful to skirt?

GregAC

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Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 name:   // TODO: This needs deciding upon. Eventually, it might be nice to allow this   //       to be overridden on the command line ("I've got a bunch of ELF files   //       that stress my new feature; please run the test suite with them")-  otbn_elf_dir: "{sw_build_dir}"-+  otbn_elf_dir: "{run_dir}/build-out"   run_opts: ["+otbn_elf_dir={otbn_elf_dir}"] +  // OTBN run modes.+  run_modes: [+    {+      name: build_otbn_rig_binaries_mode+      pre_run_cmds: ["BUILD_ROOT={run_dir} cd {proj_root} && ./meson_init.sh",+                     "{proj_root}/hw/ip/otbn/dv/uvm/gen-binaries.py --seed {seed} {otbn_elf_dir}"]

No, but I can teach it that trick. I'll come back to this next week.

sriyerg

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Pull request review commentlowRISC/ibex

Ibex fcov v3

 module ibex_controller #(     end   end +  //////////+  // FCOV //+  //////////+  `FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN));+  `FCOV_SIGNAL(logic, debug_entry_if, (ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF));+  `FCOV_SIGNAL(logic, debug_entry_id, (ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID));+  `FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH));

Yeah, I'm not sure what's better there. About FCOV_UNUSED, I think you probably want a unary XOR (Michael Schaffner pointed this out to me in the past). As I understand it, the problem with a unary OR is that some tools get upset if it they manage to prove that one of the bits is always true and then throw away the lot.

GregAC

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Pull request review commentlowRISC/opentitan

[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

 name:   // TODO: This needs deciding upon. Eventually, it might be nice to allow this   //       to be overridden on the command line ("I've got a bunch of ELF files   //       that stress my new feature; please run the test suite with them")-  otbn_elf_dir: "{sw_build_dir}"-+  otbn_elf_dir: "{run_dir}/build-out"   run_opts: ["+otbn_elf_dir={otbn_elf_dir}"] +  // OTBN run modes.+  run_modes: [+    {+      name: build_otbn_rig_binaries_mode+      pre_run_cmds: ["BUILD_ROOT={run_dir} cd {proj_root} && ./meson_init.sh",+                     "{proj_root}/hw/ip/otbn/dv/uvm/gen-binaries.py --seed {seed} {otbn_elf_dir}"]

... which I think is problematic. Dvsim should not assume it is in full control of building all components of OpenTitan from source, but rely on the output from other build systems, outside of the dvsim boundary, instead. I have opened #4326 to discuss this further.

For this PR: @rswarbrick is gen-binaries.py able to cope with only $BUILD_ROOT being set, but not $OBJ_DIR, and will it set OBJ_DIR = $BUILD_ROOT/build-bin (an assumption that dvsim makes).

sriyerg

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pull request commentlowRISC/opentitan

[DV] Updates to the way SW is built for DV simulations

I had a look at the changes, and they are fine on their own. I'm however very worried about the path dvsim is taking by including the software build. I have opened https://github.com/lowRISC/opentitan/issues/4326 to discuss this further. I'm hoping we can refrain from going down the route of dvsim orchestrating more builds which cross the DV boundary until we have reached agreement on the issue I linked.

sriyerg

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issue commentlowRISC/opentitan

Specify interaction between component build systems

CC @sriyerg @msfschaffner @gkelly @lenary @rswarbrick @moidx

imphil

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issue openedlowRISC/opentitan

Specify interaction between component build systems

We currently have multiple build systems for the different components of OpenTitan, but have not finally agreed on a way how those build systems interact. This is especially critical now that we're seeing more and more chip-level work where build artifacts from different components need to be plugged together.

I have created a document outlining the status quo at https://docs.google.com/document/d/1UxT0jkrGfwvOf6KYoEnrTgWdft-aWjNCoKf06_7C05Y/edit#.

While software, FPGA and Verilator chip-level simulation builds as well as end-to-end system tests are written (and used in CI) to be called individually and build artifacts to be stored in $BIN_DIR, dvsim assumes (and expands more towards) being a "all in one" build system which operates in its own build directory structure and also, for example, triggers software builds when needed for a chip-level DV run. This leads to two ways of building components existing next to each other.

We need to clarify:

  1. How do we want the cross-component builds to happen?
  2. Are we happy with the current lack of a high-level build system, which instead relies on the developer (or CI logic) to orchestrate component builds? If not, how could a minimal solution to that problem look?
  3. Do we want dvsim to be the "high-level build system" that everybody uses? If so, what extensions would be necessary to enable parallelized and distributed multi-stage builds, as we do them in CI?

I'm proposing for everyone to have a look at the linked document and think about the problem. Please comment if you have input, and I'll then try to follow up as necessary (probably in one of the meetings, and then with a final proposal/doc change).

created time in a day

Pull request review commentlowRISC/ibex

Ibex fcov v3

+// Copyright lowRISC contributors.+// Licensed under the Apache License, Version 2.0, see LICENSE for details.+// SPDX-License-Identifier: Apache-2.0++interface core_ibex_fcov_if import ibex_pkg::*; (+  input clk_i,+  input rst_ni,++  input priv_lvl_e priv_mode_id,+  input priv_lvl_e priv_mode_if,+  input priv_lvl_e priv_mode_lsu+);+`ifdef UVM+  import uvm_pkg::*;+`endif

Oh, I see. Hmm, is import uvm_pkg::* idempotent? If so, we could fold it in to the macro?

GregAC

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Pull request review commentlowRISC/ibex

Ibex fcov v3

+// Copyright lowRISC contributors.+// Licensed under the Apache License, Version 2.0, see LICENSE for details.+// SPDX-License-Identifier: Apache-2.0++interface core_ibex_fcov_if import ibex_pkg::*; (+  input clk_i,+  input rst_ni,++  input priv_lvl_e priv_mode_id,+  input priv_lvl_e priv_mode_if,+  input priv_lvl_e priv_mode_lsu+);+`ifdef UVM+  import uvm_pkg::*;+`endif

UVM macros call UVM methods underneath, so uvm_pkg needs to be imported wherever they are invoked. Not sure there is a good way to fix this.

GregAC

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Pull request review commentlowRISC/opentitan

[DV] Updates to the way SW is built for DV simulations

 run: run_result pre_run: prep_tool_srcs 	@echo "[make]: pre_run" 	mkdir -p ${run_dir}-ifneq (${sw_test},)-	mkdir -p ${sw_build_dir}-endif +.ONESHELL: sw_build: pre_run 	@echo "[make]: sw_build"-ifneq (${sw_test},)+ifneq (${sw_images},)+	set -e+	mkdir -p ${sw_build_dir} 	# Initialize meson build system.-	${LOCK_SW_BUILD} "cd ${proj_root} && \+	${LOCK_SW_BUILD_DIR} "cd ${proj_root} && \ 		BUILD_ROOT=${sw_build_dir} ${proj_root}/meson_init.sh"-	# Compile boot rom code and generate the image.-	${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \-		sw/device/boot_rom/boot_rom_export_${sw_build_device}"-	# Extract the boot rom logs.-	${proj_root}/util/device_sw_utils/extract_sw_logs.py \-		-e "${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.elf" \-		-f .logs.fields -r .rodata .chip_info \-		-n "rom" -o "${run_dir}"-	# Copy over the boot rom image to the run_dir.-	cp ${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.32.vmem \-		${run_dir}/rom.vmem-	cp ${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.elf \-		${run_dir}/rom.elf--ifeq (${sw_test_is_prebuilt},1)-	# Copy over the sw test image and related sources to the run_dir.-	cp ${proj_root}/${sw_test}.64.vmem ${run_dir}/sw.vmem-	# Optionally, assume that ${sw_test}_logs.txt exists and copy over to the run_dir.-	# Ignore copy error if it actually doesn't exist. Likewise for ${sw_test}_rodata.txt.-	-cp ${proj_root}/${sw_test}_logs.txt ${run_dir}/sw_logs.txt-	-cp ${proj_root}/${sw_test}_rodata.txt ${run_dir}/sw_rodata.txt--else-	# Compile the sw test code and generate the image.-	${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \-		${sw_test}_export_${sw_build_device}"-	# Convert sw image to frame format-	# TODO only needed for loading sw image through SPI. Can enhance this later-	${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out sw/host/spiflash/spiflash_export"-	${LOCK_SW_BUILD} "${sw_build_dir}/build-bin/sw/host/spiflash/spiflash --input \-		${sw_build_dir}/build-bin/${sw_test}_${sw_build_device}.bin \-		--dump-frames=${run_dir}/sw.frames.bin"-	${LOCK_SW_BUILD} "srec_cat ${run_dir}/sw.frames.bin --binary \-		--offset 0x0 --byte-swap 4 --fill 0xff -within ${run_dir}/sw.frames.bin -binary -range-pad 4 \-		--output ${run_dir}/sw.frames.vmem --vmem"-	# Extract the sw test logs.-	${proj_root}/util/device_sw_utils/extract_sw_logs.py \-		-e "${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.elf" \-		-f .logs.fields -r .rodata \-		-n "sw" -o "${run_dir}"-	# Copy over the sw test image to the run_dir.-	cp ${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.64.vmem ${run_dir}/sw.vmem-	cp ${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.elf ${run_dir}/sw.elf-endif +	# Loop through the list of sw_images and invoke meson on each item.+	# `sw_images` is a list of tests to be built into an image, separated by space.+	# Optionally, each item in the list can have additional info supplied using+	# delimiter ':'. The format is as follows:+	# <path-to-sw-test>:<index>:<flag>+	#+	# If no delimiter is detected, then the full string is considered to be the+	# <path-to-sw-test>. If 1 delimiter is detected, then it must be <path-to-sw-+	# test> followed by <index>. The <flag> is considered optional.+	@for sw_image in ${sw_images}; do \+		image=`echo $$sw_image | cut -d: -f 1`;  \+		index=`echo $$sw_image | cut -d: -f 2`; \+		flags=(`echo $$sw_image | cut -d: -f 3- --output-delimiter " "`); \+		if [[ -z $$image ]]; then \+			echo "ERROR: SW image \"$$sw_image\" is malformed."; \+			echo "Expected format: index::path-to-sw-test:optional-flag."; \

Good catch! Fixed.

sriyerg

comment created time in a day

pull request commentlowRISC/opentitan

[DV] Updates to the way SW is built for DV simulations

LGTM (with one nit, below).

We might be using build_by_default: true in too many places, but let's leave evaluating that for a follow-up change, as I'm not sure we have a principle behind when we allow that. I don't think it matters for this PR, this PR is about establishing the dependency graph correctly for DV.

Aah yes, you're right. Its not really needed on these target since they are intermediate. I will go ahead and remove them.

sriyerg

comment created time in a day

push eventlowRISC/opentitan

Srikrishna Iyer

commit sha 6c531b093be8ce22ecd537e5f45a7430a877204b

[DVSim] Method to add pre/post build/run steps Skeletal support for being able to run additional DUT-specific pre/post build/run commands existed in DVSim, but there wasn't a need to fully support it until now. To support the OTBN build-some-binaries before running the simulations usecase, this commit adds the ability to supply the following information: `pre_build_cmds`, `post_build_cmds`, `pre_run_cmds` & `post_run_cmds`. These are list variables that can be set in the following places: 1. Bare, within the HJson (all 4 of them) 2. Within build modes (all 4 of them) 3. Within run modes (only pre/post_run_cmds) 4. In regressions (all 4 of them) 5. In test specifications (only pre/post_run_cmds) Each of these places limits on which builds / tests will they get invoked, enabling a finer control of setting these commands. If these are set inside modes, then all mode-specific functionality still holds (modes can enable other modes, etc). During processing, if these lists are encountered more than once, they get appended together. It is the users responsibility to ensure ordering if required. Before these are supplied to GNUMake, all commands in each of these lists are appended with ' && ' so that they are chained together as a single command when Make invokes them in a subshell. This is done to ensure Make halts if any one of them fails. Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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Srikrishna Iyer

commit sha eb4bc1bd8de18535aefd37ab97004585fa400beb

[OTBN DV] Prototype impl of gen-binaries This builds on top of the previous commit to generate some binaries for a test and a pre-run step. This is suitable in terms of reproducability and wider coverage since the test seed is also passed on to the RIG binary generator script. The downside of this approach is the generator is invoked for each and every seed of each and every test that needs it, which could be an overkill. It however does not seem to be a strain o the simulation time though. If a post build step is desired instead, then that can also be achieved by moving the commands to `post_build_cmds` variable placed bare in the HJSon to ensure it is executed for all available builds. The paths of course, will need to be updated. The downside of this is the `--seed` switch of the script would have to be foregoed. Signed-off-by: Srikrishna Iyer <sriyer@google.com>

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PR merged lowRISC/opentitan

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[dvsim, OTBN] Ability to execute arbitrary pre/post build/run commands & working OTBN smoke test

The first commit enhances DVSim to be able to add pre/post build and run commands art various levels.

The second updates OTBN DV to add the binary generation as a pre-run step.

+110 -30

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5 changed files

sriyerg

pr closed time in a day

issue closedlowRISC/opentitan

[dvsim] Add support for running arbitrary commands before / after builds and runs

This is needed to support OTBN, which requires some binaries to be built before launching a simulation run.

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sriyerg
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