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chipsalliance/Surelog 158

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

chipsalliance/UHDM 72

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

antmicro/tuttest 6

A simple Python utility for extracting documentation snippets from tutorials.

antmicro/fusesoc-verible-demo 5

FuseSoC and Verible integration demo

JPETTomography/Gate 0

Modification of GATE code for simulation of ortho-positronium annihilation

JPETTomography/j-pet-mlem 0

MLEM implementation for J-PET

JPETTomography/j-pet-mlem-old 0

MLEM implementation for J-PET

kamilrakoczy/3d-game-engine 0

Simple 3d game engine

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Pull request review commentJPETTomography/j-pet-gate-tools

Adjust GOJA to benchmark data

 void EventAnalysis::select_coincident_hits(vector<Hit> &hits) {  } +void EventAnalysis::select_coincident_singles(vector<Hit> &hits) {++  bool debug = true; // TODO: rmove

Should this be removed before PR?

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pull request commentantmicro/yosys-uhdm-plugin-integration

Bump sv2v from `88d632f` to `e42fbfa`

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Pull request review commentantmicro/yosys

Yosys multiranges

+package pkg;+parameter int unsigned Num  = 4;+endpackage++module mdia(+  input logic [pkg::Num-1:0][pkg::Num-1:0] var1_i,+  input logic [3:0][3:0][7:0] var2_i,+  output logic [3:0][3:0][7:0] var3_o+);+  logic [3:0][3:0][7:0] out;+  assign out[1][1][2] = 1'b1;+  assign out[2][1][2] = 1'b0;+  assign var3_o = out;++always_comb begin+  assert(var1_i[0][0] == 1'b1);+  assert(var1_i[3][2] == 1'b0);+  assert(var2_i[0][0][0] == 1'b0);+  assert(var2_i[2][1][3] == 1'b1);+end+endmodule++module dut();+parameter [3:0][3:0][7:0] PackedParam = 8'b11000011;+localparam [3:0][3:0][7:0] LocalPackedParam = 8'b11000011;++logic [pkg::Num-1:0][pkg::Num-1:0] var1;+logic [3:0][3:0][7:0] var2;+logic [3:0][3:0][7:0] var3;++logic [3:0][3:0][7:0] var4;+logic [3:0][3:0][7:0] var5;++assign var1[0][0] = 1'b1;+assign var1[3][2] = 1'b0;++assign var2[0][0][0] = 1'b0;+assign var2[2][1][3] = 1'b1;++assign var4 = PackedParam;+assign var5 = LocalPackedParam;++mdia md(var1, var2, var3);++always_comb begin+  assert(var3[1][1][2] == 1'b1);+  assert(var3[2][1][2] == 1'b0);+  assert(var4 == PackedParam);+  assert(var5 == LocalPackedParam);+end++endmodule

Please also add check that:

logic [3:0] mtimecmp         [1][1];

is working and mtimecmp[0] is selecting whole 4 bits (not just 1).

pawelsag

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Pull request review commentantmicro/yosys

Yosys multiranges

+typedef struct packed {+  logic a_p;+  logic a_n;+} pinout_t;+++typedef struct packed {+   logic [1:0] s1;+   logic [2:0] s2;+   logic       s3;+} parity_t;++typedef struct packed {+   logic                  [2:0]   var1;+   logic                  [2:0]   var2;+   parity_t                       var3;+} complex_struct_t;++parameter int Size = 4;++module dut();++logic [3:0][3:0][7:0] multirange_logic;+logic [15:0] multirange_logic_cpy;++pinout_t [Size*2-1:0] pinout = 8'b10110010;+logic [2:0] pinout_part_cpy;++complex_struct_t complex_hw [3];+complex_struct_t complex_hw_cpy;++pinout_t[1:0][1:0] complex_hw_multirange[2:0][1:0];+pinout_t[1:0][1:0] hw_multirange_cpy[2:0][1:0];++localparam int N_HARTS  = 2;+localparam int N_TIMERS = 1;+logic [3:0] mtime            [N_HARTS];+logic [3:0] mtimecmp         [N_HARTS][N_TIMERS];+logic       mtimecmp_update  [1][1];++assign multirange_logic[3][3:2] = 16'b1010101010101010;+assign multirange_logic[3][1:0] = 16'b0000000000000000;++assign multirange_logic_cpy = multirange_logic[3][2:1];++assign pinout_part_cpy = pinout[4:2];++assign complex_hw[1] = 12'b110010011100;+assign complex_hw_cpy = complex_hw[1];++assign complex_hw_multirange = 48'b100101100101100101100101100101100101100101100101;+assign hw_multirange_cpy = complex_hw_multirange;++assign mtime[0] = 4'b1100;+assign mtime[1] = 4'b0011;++assign mtimecmp_update[0][0] = 1;++assign mtimecmp[0][0][3:2] = mtime[0][3:2];+assign mtimecmp[1][0][1:0] = mtime[1][1:0];++always_comb begin+  assert(multirange_logic_cpy == 16'b1010101000000000);++  assert(pinout_part_cpy == 3'b100);++  assert(complex_hw_cpy == 12'b110010011100);++  assert(mtimecmp[0][0][3:2] == mtimecmp[1][0][1:0]);+  assert(mtimecmp_update[0][0] == 1);++  assert(complex_hw_cpy == complex_hw[1]);++  assert(complex_hw_cpy[3] == 1);+  assert(complex_hw_cpy[3] != 0);

This asserts exclude each other (if complex_hw_cpy[3] is equal 1 it must not be equal to 0). Please keep only first check, as it is more specific.

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pull request commentantmicro/yosys-uhdm-plugin-integration

Bump Surelog from `ff28a2e` to `d459cee`

@dependabot rebase

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Kamil Rakoczy

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Move alert_handler_reg_top and alert_handler_reg_wrap to uhdm Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

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Move clkgen to uhdm Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

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Remove notneeded patch Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

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Bump yosys-symbiflow-plugins Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

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PR merged antmicro/yosys-uhdm-plugin-integration

Reviewers
Move alert_handler, top_earlgrey, clkgen, jtag_mux and top_earlgrey_nexysvideo to UHDM

Move alert_handler, top_earlgrey, clkgen, jtag_mux and top_earlgrey_nexysvideo to UHDM. Fixes: https://github.com/chipsalliance/UHDM-integration-tests/issues/277 Fixes: https://github.com/chipsalliance/UHDM-integration-tests/issues/218 Now all modules are only parsed by UHDM.

+11778 -13118

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kamilrakoczy

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issue closedchipsalliance/UHDM-integration-tests

Earlgrey: bitstream doesn't work after parsing prim_clock_gating

prim_clock_gating module is used both in ibex_core and clkmgr modules. It can only be moved to Surelog, when both of these modules will also be moved to Surelog, without this generated bitstream is not working on HW.

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kamilrakoczy

issue closedchipsalliance/UHDM-integration-tests

Earlgrey: alert_handler_reg_top doesn't work in yosys

alert_handler_reg_top.sv file requires aes_reg_pkg.sv but this file is currently not working in yosys: https://github.com/alainmarcel/uhdm-integration/issues/274

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kamilrakoczy

PR opened hdl/conda-eda

WIP: yosys-uhdm: fix missing libffi in host

This PR tries to fix: libffi.so.7: cannot open shared object file: No such file or directory: https://github.com/chipsalliance/sv-tests/issues/1758

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