verilog-to-routing/vtr-verilog-to-routing 427
Verilog to Routing -- Open Source CAD Flow for FPGA Research
SymbiFlow/vtr-verilog-to-routing 24
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
SymbiFlow/sphinxcontrib-markdown-symlinks 2
Python library to solve markdown cross-reference links when building sphinx documentation
SymbiFlow/symbiflow-tools-data-manager 2
Python based package manager to get packages and artifacts of symbiflow projects
SymbiFlow/symbiflow-xc-fasm2bels 2
Library to convert a FASM file into BELs importable into Vivado.
SymbiFlow/symbiflow-rr-graph 1
Collection of Routing Resources Graph (RR Graph) libraries for VPR
Conda build recipes for the toolchains needed by LiteX / MiSoC firmware
Experimental flows using nextpnr for Xilinx devices
Project X-Ray Database: XC7 Series
delete branch SymbiFlow/symbiflow-arch-defs
delete branch : dependabot/submodules/third_party/liteiclink-547a699
delete time in 4 hours
PR closed SymbiFlow/symbiflow-arch-defs
Bumps third_party/liteiclink from 63987bf to 547a699.
<details>
<summary>Commits</summary>
<ul>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/547a6994a34912f29a038ef8f8aae3b2857a7da8"><code>547a699</code></a> bench/serdes: use 20-bit datapath for all targets, simplify.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/87bb52537e91964f155f184f39512bc407c00277"><code>87bb525</code></a> serdes/serdes_ecp5: revert old COMMA_MASK/A/B values (fix loopback).</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/efe862b7e20fcf1e71f1c0860738398aea2aa127"><code>efe862b</code></a> bench/serdes/targets: add identifier, use platforms from litex_boards and fix...</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/20efbb6db6f79c8923f5d4d65148bc7c08dc2b41"><code>20efbb6</code></a> bench/serdes: remove pcie_sceamer.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/65b5193b570dde3ce5b1d2305e61fc415741f15f"><code>65b5193</code></a> bench/serdes: add trellisboard target based on versa_ecp5.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/fb77360ee82c3944ebcb69dacdca48e10cddd6b1"><code>fb77360</code></a> serdes/serdes_ecp5: replace RTERM_RX/TX, COMMA_A/B binary values with decimal...</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/3d1165b489e419955a25633acc45e1f68ac0006f"><code>3d1165b</code></a> serdes/gtp_7series: set TXDLYEN to 0 when tx_buffer_enable.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/82ff0dd9c99b248fd23c750bb25c86353d15e498"><code>82ff0dd</code></a> serdes/GTPRXInit: fix duplicate state name and use plllock.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/bd8231c9b7373d3ef2866382db3360e820a5494d"><code>bd8231c</code></a> bench/serwb: add ulx3s target.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/2eb3f608b29b635554e6c9c69a3743933e4ac25e"><code>2eb3f60</code></a> serwb/test_serwb: add simple access test.</li>
<li>Additional commits viewable in <a href="https://github.com/enjoy-digital/liteiclink/compare/63987bf4e2d680518eb2e15aafe46163bc7f7b92...547a6994a34912f29a038ef8f8aae3b2857a7da8">compare view</a></li>
</ul>
</details>
<br />
Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase.
<details> <summary>Dependabot commands and options</summary> <br />
You can trigger Dependabot actions by commenting on this PR:
@dependabot rebasewill rebase this PR@dependabot recreatewill recreate this PR, overwriting any edits that have been made to it@dependabot mergewill merge this PR after your CI passes on it@dependabot squash and mergewill squash and merge this PR after your CI passes on it@dependabot cancel mergewill cancel a previously requested merge and block automerging@dependabot reopenwill reopen this PR if it is closed@dependabot closewill close this PR and stop Dependabot recreating it. You can achieve the same result by closing it manually@dependabot ignore this major versionwill close this PR and stop Dependabot creating any more for this major version (unless you reopen the PR or upgrade to it yourself)@dependabot ignore this minor versionwill close this PR and stop Dependabot creating any more for this minor version (unless you reopen the PR or upgrade to it yourself)@dependabot ignore this dependencywill close this PR and stop Dependabot creating any more for this dependency (unless you reopen the PR or upgrade to it yourself)@dependabot use these labelswill set the current labels as the default for future PRs for this repo and language@dependabot use these reviewerswill set the current reviewers as the default for future PRs for this repo and language@dependabot use these assigneeswill set the current assignees as the default for future PRs for this repo and language@dependabot use this milestonewill set the current milestone as the default for future PRs for this repo and language@dependabot badge mewill comment on this PR with code to add a "Dependabot enabled" badge to your readme
Additionally, you can set the following in your Dependabot dashboard:
- Update frequency (including time of day and day of week)
- Pull request limits (per update run and/or open at any time)
- Automerge options (never/patch/minor, and dev/runtime dependencies)
- Out-of-range updates (receive only lockfile updates, if desired)
- Security updates (receive only security updates, if desired)
</details>
pr closed time in 4 hours
pull request commentSymbiFlow/symbiflow-arch-defs
build(deps): bump third_party/liteiclink from `63987bf` to `547a699`
Superseded by #1805.
comment created time in 4 hours
create barnchSymbiFlow/symbiflow-arch-defs
branch : dependabot/submodules/third_party/liteiclink-cc19a26
created branch time in 4 hours
PR opened SymbiFlow/symbiflow-arch-defs
Bumps third_party/liteiclink from 63987bf to cc19a26.
<details>
<summary>Commits</summary>
<ul>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/cc19a26c49e9e655babed8c7a2948df73fef7f4c"><code>cc19a26</code></a> ci: migrate from Travis CI to Github Actions.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/547a6994a34912f29a038ef8f8aae3b2857a7da8"><code>547a699</code></a> bench/serdes: use 20-bit datapath for all targets, simplify.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/87bb52537e91964f155f184f39512bc407c00277"><code>87bb525</code></a> serdes/serdes_ecp5: revert old COMMA_MASK/A/B values (fix loopback).</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/efe862b7e20fcf1e71f1c0860738398aea2aa127"><code>efe862b</code></a> bench/serdes/targets: add identifier, use platforms from litex_boards and fix...</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/20efbb6db6f79c8923f5d4d65148bc7c08dc2b41"><code>20efbb6</code></a> bench/serdes: remove pcie_sceamer.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/65b5193b570dde3ce5b1d2305e61fc415741f15f"><code>65b5193</code></a> bench/serdes: add trellisboard target based on versa_ecp5.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/fb77360ee82c3944ebcb69dacdca48e10cddd6b1"><code>fb77360</code></a> serdes/serdes_ecp5: replace RTERM_RX/TX, COMMA_A/B binary values with decimal...</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/3d1165b489e419955a25633acc45e1f68ac0006f"><code>3d1165b</code></a> serdes/gtp_7series: set TXDLYEN to 0 when tx_buffer_enable.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/82ff0dd9c99b248fd23c750bb25c86353d15e498"><code>82ff0dd</code></a> serdes/GTPRXInit: fix duplicate state name and use plllock.</li>
<li><a href="https://github.com/enjoy-digital/liteiclink/commit/bd8231c9b7373d3ef2866382db3360e820a5494d"><code>bd8231c</code></a> bench/serwb: add ulx3s target.</li>
<li>Additional commits viewable in <a href="https://github.com/enjoy-digital/liteiclink/compare/63987bf4e2d680518eb2e15aafe46163bc7f7b92...cc19a26c49e9e655babed8c7a2948df73fef7f4c">compare view</a></li>
</ul>
</details>
<br />
Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase.
<details> <summary>Dependabot commands and options</summary> <br />
You can trigger Dependabot actions by commenting on this PR:
@dependabot rebasewill rebase this PR@dependabot recreatewill recreate this PR, overwriting any edits that have been made to it@dependabot mergewill merge this PR after your CI passes on it@dependabot squash and mergewill squash and merge this PR after your CI passes on it@dependabot cancel mergewill cancel a previously requested merge and block automerging@dependabot reopenwill reopen this PR if it is closed@dependabot closewill close this PR and stop Dependabot recreating it. You can achieve the same result by closing it manually@dependabot ignore this major versionwill close this PR and stop Dependabot creating any more for this major version (unless you reopen the PR or upgrade to it yourself)@dependabot ignore this minor versionwill close this PR and stop Dependabot creating any more for this minor version (unless you reopen the PR or upgrade to it yourself)@dependabot ignore this dependencywill close this PR and stop Dependabot creating any more for this dependency (unless you reopen the PR or upgrade to it yourself)@dependabot use these labelswill set the current labels as the default for future PRs for this repo and language@dependabot use these reviewerswill set the current reviewers as the default for future PRs for this repo and language@dependabot use these assigneeswill set the current assignees as the default for future PRs for this repo and language@dependabot use this milestonewill set the current milestone as the default for future PRs for this repo and language@dependabot badge mewill comment on this PR with code to add a "Dependabot enabled" badge to your readme
Additionally, you can set the following in your Dependabot dashboard:
- Update frequency (including time of day and day of week)
- Pull request limits (per update run and/or open at any time)
- Automerge options (never/patch/minor, and dev/runtime dependencies)
- Out-of-range updates (receive only lockfile updates, if desired)
- Security updates (receive only security updates, if desired)
</details>
pr created time in 4 hours
pull request commentverilog-to-routing/vtr-verilog-to-routing
rr_graph: avoide div-by-zero issues while getting the delay norm fac
LGTM. Whenever CI goes green this can be merged.
comment created time in 10 hours
issue closedSymbiFlow/fpga-tool-perf
No meta.json file is produced on failure
It's useful to have data from the tests that succeeded, even if some of them fail.
closed time in 11 hours
HackerFoo
issue commentSymbiFlow/fpga-tool-perf
No meta.json file is produced on failure
They only seem to be missing for the failed builds; successful builds do have a meta.json file.
comment created time in 11 hours
push eventantmicro/prjxray
commit sha b2db490a62c039212bcc7c599d3b6b1bf50eb32b
Enable partial bitstream generation for Series7 Signed-off-by: Jan Kowalewski <[email protected]>
commit sha 564b5ae34be355f1543ab7705afad93d6c79d3f0
Add partial bitstream generation support to xc7frames2bit Signed-off-by: Jan Kowalewski <[email protected]>
commit sha afba219e899b2f95555404a5d29076dab6d07b8f
[WIP] Add partial bitstream test
push time in 12 hours
PR opened SymbiFlow/prjxray
This PR fixes the missing symbolic links generation during building the Sphinx documentation
Resolves https://github.com/SymbiFlow/prjxray/issues/1504
pr created time in 15 hours
push eventantmicro/prjxray
commit sha 09da8c7738214af9d2e82e97f27b8e3bbc2ad5dd
doc: Fix links generation for markdown-code-symlinks Signed-off-by: Robert Winkler <[email protected]>
push time in 15 hours
issue commentSymbiFlow/prjxray
Inconsistent project documentation?
@mithro It was more that on Prjxray docs, after "fuzzers", "minitests", "tools", then my new "Guide.." appeared. On Symbiflow docs, my new "Guide..." doesn't appear at the same point. So perhaps I need to find another file in which to add a link to the new guide.
comment created time in 15 hours
push eventantmicro/prjxray
commit sha 9a30393196e8c3ec0c1c431471172c64d340f868
doc: Fix links generation for markdown-code-symlinks Signed-off-by: Robert Winkler <[email protected]>
push time in 15 hours
issue commentSymbiFlow/prjxray
Inconsistent project documentation?
Probably this is due to missing links in the documentation when building on RTD: https://github.com/SymbiFlow/symbiflow-docs/blob/master/source/conf.py#L348
I will check that
comment created time in 15 hours
issue commentSymbiFlow/prjxray
Inconsistent project documentation?
@tcal-x - This is what you discovered?
comment created time in 15 hours
issue openedSymbiFlow/prjxray
Inconsistent project documentation?
The prjxray sphinx docs should be identical when viewed;
- Directly via prjxray
- When part of the symbiflow documentation
The documentation when viewed at https://symbiflow.readthedocs.io/projects/prjxray/en/latest/# has a fairly short list under items;
Yet, when you view the documentation at https://symbiflow.readthedocs.io/en/latest/ you get a much longer output;
created time in 15 hours
pull request commentSymbiFlow/symbiflow-arch-defs
Make Ibex sv2v conversion deterministic
Can you do another rebase? That should make the VtR + SymbiFlow Architecture Definitions (Presubmit) builder go away.
comment created time in 16 hours
issue commentSymbiFlow/symbiflow-arch-defs
Litex: drop the --symbiflow flag when generating the minilitex design
There are two potential locations that have bugs,
- Bug is in Yosys SDC generation -- the yosys plugin is generating a SDC file which refers to a net which does not exists in in the blif.
- Bug in VPR -- The net appears in the blif and VPR is sweeping the net and not sweeping the SDC too (as @litghost mentions).
comment created time in 16 hours
issue commentSymbiFlow/fpga-tool-perf
Ok I've found the issue. These features conflict for segbits_cmt_top_r_upper_t but not for segbits_cmt_top_l_upper_t.
comment created time in 16 hours
push eventantmicro/prjxray
commit sha 6212c4a73cab16658d8355e6779e5aa9d731a504
WIP partial support
push time in 17 hours
pull request commentverilog-to-routing/vtr-verilog-to-routing
rr_graph: avoide div-by-zero issues while getting the delay norm fac
Would returning 0 result in 0 base costs? If so, I think it's better to return 1 or 1e-9 (1 ns) if this happens. Since we're issuing a warning and continuing we should make sure the returned value will let routing complete.
comment created time in 17 hours
issue commentSymbiFlow/fpga-tool-perf
@acomodi This is weird. These two FASM features do not even refer to the same segbits. Can you point me out to the design?
comment created time in 17 hours
pull request commentSymbiFlow/prjxray
bitread: Don't overwrite last frame
Analyzed the case with bits2rbt and bitread (with aux support required for bits2rbt) (PR) To compare the original RBF (vivado generated) with the reconstructed (bits2rbt generated).
Without the fix, ie where the bits files are equal the RBF test fails:
573766c573766
< 00000000000000001000000000000000
---
> 00000000000000000000000000000000
573866c573866
< 11111000101000010111101101110000
---
> 00100010000001110101000101010000
bits2rbt_bram_xc7 FAIL
clearly there is one missing bit (bit_00c0017f_004_15) which causes the CRC value to be invalid
With the fix the bit bit_00c0017f_004_15 is in bits, but the RBT comparison fails on different CRCs:
573812c573812
< 00000000000000000000000000000000
---
> 00000000000000000001001110101111
573866c573866
< 11111000101000010111101101110000
---
> 01000011101111001000011010011110
573871a573872
> 00000000000000001000000000000000
573917,573918c573918
< 00000000000000000000000000000000
< 00000000000000000000000000000000
---
> 00000000000000000001001110101111
573972c573972
< 00100010000001110101000101010000
---
> 01000011101111001000011010011110
comment created time in 17 hours
issue commentSymbiFlow/symbiflow-arch-defs
I have a finding. So the CMT_TOP_L_UPPER_T PIPs with missing bits are actually bi-directional pseudo PIPs. For example we have an entry in the db for CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS but we do not have one for CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS.PLL_CLK_FREQ_BB_BUFOUT_NS3.
I'm not entirely sure how we model bi-directional PIPs in VPR.
One solution that comes into my mind is to have two entries per bi-dir PPIP for both directions.
comment created time in 18 hours
Pull request review commentSymbiFlow/symbiflow-examples
To build the litex example, run the following commands: .. code:: bash :name: xc7-litex - wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py- chmod +x litex_setup.py- ./litex_setup.py init- ./litex_setup.py install wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz tar -xf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/- pushd litex/litex/boards/targets && ./arty.py --toolchain symbiflow --cpu-type vexriscv --build && popd+ pushd xc7/litex_demo && make clean && TARGET="arty_50" make && popd
All the examples have instructions for bitstream generation for various boards in the same block.
comment created time in 18 hours
Pull request review commentSymbiFlow/symbiflow-examples
+#!/usr/bin/env python3++import os+import argparse++from litex.boards.targets.arty import _CRG+from liteeth.phy.mii import LiteEthPHYMII+from litex.soc.cores.led import LedChaser++from litex.boards.platforms import arty+from litex.soc.integration.soc_core import SoCCore+from litex.soc.integration.builder import Builder+from litex.soc.integration.soc_core import soc_core_args, soc_core_argdict+from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict++# TODO: Add SDRAM support for SymbiFlow Toolchain:
fixed with https://github.com/enjoy-digital/litex/pull/704
comment created time in 18 hours
Pull request review commentSymbiFlow/symbiflow-examples
python-constraint git+https://github.com/symbiflow/fasm git+https://github.com/symbiflow/xc-fasm+
fixed
comment created time in 18 hours
Pull request review commentSymbiFlow/symbiflow-examples
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
added
comment created time in 18 hours
Pull request review commentSymbiFlow/symbiflow-tools-data-manager
stdm: add possibility to get multiple urls for a single build
def main(): help="Name of the jobset. Can choose between presubmit and continous", ) parser.add_argument(- "--get_max_int",+ "--get_build_number",+ action="store_true",+ help="Retrieve the CI build number",+ )+ parser.add_argument(+ "--get_single_url",+ action="store_true",+ help="Retrieve a single random URL from a given build",+ )+ parser.add_argument(+ "--get_all_urls", action="store_true",- help="Retrieve also the CI build number",+ help="Retrieve all the URLs of a given build", ) args = parser.parse_args() - print(- get_latest_artifact_url(- args.project, args.build_name, args.jobset, args.get_max_int+ if not (args.get_all_urls ^ args.get_single_url ^ args.get_build_number):
this may be confusing - it will enable single_url even if all the parameters are set (or none of them is). Also the following combination will enable single_url:
all_urls = True, single_url= False,build_number` = True
so user explicitly don't want single_url but the code will enable it
comment created time in 19 hours