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joker-eph/mlir 0

"Multi-Level Intermediate Representation" Compiler Infrastructure

River707/llvm-project 0

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

River707/mlir 0

"Multi-Level Intermediate Representation" Compiler Infrastructure

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commit sha a82b63a7411b34e0e6d4e96d4d2c2deaeb266e47

[mlir][DialectConversion] Forward capture callback to fix build on older GCC Older GCC confuses the type of 'callback' after it gets captured, so add a forward capture to move it properly.

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commit sha 0d7ff220ed0eeffda3839546ac1f30e98f60128e

[mlir] Refactor TypeConverter to add conversions without inheritance Summary: This revision refactors the TypeConverter class to not use inheritance to add type conversions. It instead moves to a registration based system, where conversion callbacks are added to the converter with `addConversion`. This method takes a conversion callback, which must be convertible to any of the following forms(where `T` is a class derived from `Type`: * Optional<Type> (T type) - This form represents a 1-1 type conversion. It should return nullptr or `llvm::None` to signify failure. If `llvm::None` is returned, the converter is allowed to try another conversion function to perform the conversion. * Optional<LogicalResult>(T type, SmallVectorImpl<Type> &results) - This form represents a 1-N type conversion. It should return `failure` or `llvm::None` to signify a failed conversion. If the new set of types is empty, the type is removed and any usages of the existing value are expected to be removed during conversion. If `llvm::None` is returned, the converter is allowed to try another conversion function to perform the conversion. When attempting to convert a type, the TypeConverter walks each of the registered converters starting with the one registered most recently. Differential Revision: https://reviews.llvm.org/D74584

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commit sha 94a4ca4bf33b0c536bb22f09e035a2df24b0776f

[mlir] Add a TypeRange class that functions similar to ValueRange. Summary: This class wraps around the various different ways to construct a range of Type, without forcing the materialization of that range into a contiguous vector. Differential Revision: https://reviews.llvm.org/D74646

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commit sha 7a551600d1af561e91f7f66210d1ffd588c426fd

[mlir] Address post commit feedback of D73590 for SymbolsAndSymbolTables.md

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riverriddle@google.com

commit sha 857b655d7aac50462ffd0154b9d6c4f18119ddfb

[mlir] Allow adding extra class declarations to interfaces. Summary: This matches the similar feature on operation definitions. Reviewers: jpienaar, antiagainst Reviewed By: jpienaar, antiagainst Subscribers: mehdi_amini, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74438

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commit sha 9b07512fd3cd4541872dd2e96a697172f3f7a243

[mlir][Parser][NFC] Remove several usages of getEncodedSourceLocation Summary: getEncodedSourceLocation can be very costly to compute, especially if the input line becomes very long. This revision inlines some of the verification of a few `getChecked` methods to avoid the materialization of an encoded source location. Differential Revision: https://reviews.llvm.org/D74587

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Uday Bondhugula

commit sha 2101590a78b7189f89aa06513eeea2dee6a3c45a

NFC: add indexing operator for ArrayAttr Summary: - add ArrayAttr::operator[](unsigned idx) Differential Revision: https://reviews.llvm.org/D74663

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commit sha 5756bc4382a6023c8dcc25f39243a49ac413f9bf

[mlir][DeclarativeParser] Add support for formatting enum attributes in the string form. Summary: This revision adds support to the declarative parser for formatting enum attributes in the symbolized form. It uses this new functionality to port several of the SPIRV parsers over to the declarative form. Differential Revision: https://reviews.llvm.org/D74525

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commit sha c74150e75f69de88bb18b0ed636465db1bae23b4

[mlir][ODS][NFC] Mark OpaqueType as a buildable type. This allows for using it in the declarative assembly form, among other things.

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commit sha a134ccbbebe6e4e7cfd11a5583a7e1786a22505a

[mlir][DeclarativeParser] Move operand type resolution into a functor to share code. This reduces the duplication for the two different cases.

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commit sha c832145960736a7d531d264dcba59967d38bfc81

[mlir] Allow constructing a ValueRange from an ArrayRef<BlockArgument> Summary: This was a missed case when ValueRange was originally added, and allows for constructing a ValueRange from the arguments of a block. Differential Revision: https://reviews.llvm.org/D74363

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commit sha 52086f802e37fbb2acc61c49120990b0b3fd10cd

[llvm][TableGen] Define FieldInit::isConcrete overload Summary: There are a few field init values that are concrete but not complete/foldable (e.g. `?`). This allows for using those values as initializers without erroring out. Example: ``` class A { string value = ?; } class B<A impl> : A { let value = impl.value; // This currently emits an error. let value = ?; // This doesn't emit an error. } ``` Differential Revision: https://reviews.llvm.org/D74360

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commit sha 1b2c16f2ae41eff124a11b8a5c343fb7688a2a85

[mlir][DeclarativeParser] Add support for attributes with buildable types. This revision adds support in the declarative assembly form for printing attributes with buildable types without the type, and moves several more parsers over to the declarative form. Differential Revision: https://reviews.llvm.org/D74276

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commit sha 2f94ce0dcfd1f827105ac3d53d870447a25d57a3

[mlir][DeclarativeParser] Move several missed parsers over to the declarative form. Differential Revision: https://reviews.llvm.org/D74283

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commit sha abe3e5babdad001100b285d188e63f76fe21aea4

[mlir] Add support for generating debug locations from intermediate levels of the IR. Summary: This revision adds a utility to generate debug locations from the IR during compilation, by snapshotting to a output stream and using the locations that operations were dumped in that stream. The new locations may either; * Replace the original location of the operation. old: loc("original_source.cpp":1:1) new: loc("snapshot_source.mlir":10:10) * Fuse with the original locations as NamedLocs with a specific tag. old: loc("original_source.cpp":1:1) new: loc(fused["original_source.cpp":1:1, "snapshot"("snapshot_source.mlir":10:10)]) This feature may be used by a debugger to display the code at various different levels of the IR. It would also be able to show the different levels of IR attached to a specific source line in the original source file. This feature may also be used to generate locations for operations generated during compilation, that don't necessarily have a user source location to attach to. This requires changes in the printer to track the locations of operations emitted in the stream. Moving forward we need to properly(and efficiently) track the number of newlines emitted to the stream during printing. Differential Revision: https://reviews.llvm.org/D74019

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commit sha 5c159b91a24b07974328ab17fd56a244995f2944

[mlir] Add a utility method on CallOpInterface for resolving the callable. Summary: This is the most common operation performed on a CallOpInterface. This just moves the existing functionality from the CallGraph so that other users can access it. Differential Revision: https://reviews.llvm.org/D74250

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commit sha 20344d370403951f91e72b773090bad83bb0b328

[mlir] Add a document detailing the design of the SymbolTable. Summary: This document provides insight on the rationale and the design of Symbols in MLIR, and why they are necessary. Differential Revision: https://reviews.llvm.org/D73590

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commit sha 7476e569b55ab260522751e9c2e8c5646956f8d1

[mlir][Pass] Enable printing pass options as part of `-help`. Summary: This revision adds support for printing pass options as part of the normal help description. This also moves registered passes and pipelines into different sections of the help. Example: ``` Compiler passes to run --pass-pipeline - ... Passes: --affine-data-copy-generate - ... --convert-gpu-to-spirv - ... --workgroup-size=<long> - ... --test-options-pass - ... --list=<int> - ... --string=<string> - ... --string-list=<string> - ... Pass Pipelines: --test-options-pass-pipeline - ... --list=<int> - ... --string=<string> - ... --string-list=<string> - ... ``` Differential Revision: https://reviews.llvm.org/D74246

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commit sha 58c18ca1354ce6172b05328e6e7850a5189d6433

[mlir][AsmPrinter] Fix edge case when printing floating point values. Summary: In some edge cases the default APFloat printer will generate something that we can't parse back in. In these cases, fallback to using hex instead. Differential Revision: https://reviews.llvm.org/D74181

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commit sha 1eaa31ce0e5242dbb4c90084952bede678e360a2

[mlir][DialectConversion] Change erroneous return to a continue This fixes a nasty bug where the loop would return prematurely when notifying the argument converter that an operation was removed.

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commit sha 93dc8bd26708ba5fb8b83b65c40ed840ef76730d

[mlir] Add explicit friendship to LLVM::ModuleTranslation to derived classes. This allows for the `LLVM::ModuleTranslation::translateModule` to properly access the constructors of the derived classes.

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commit sha c3f0ed7bccaf4a62bb440ba145ada521492a1327

[mlir] Register the GDB listener with ExecutionEngine to enable debugging JIT'd code Differential Revision: https://reviews.llvm.org/D73932

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commit sha c33d6970e0172ffc6b61900c21dce8c7bda7d792

[mlir] Add support for basic location translation to LLVM. Summary: This revision adds basic support for emitting line table information when exporting to LLVMIR. We don't yet have a story for supporting all of the LLVM debug metadata, so this revision stubs some features(like subprograms) to enable emitting line tables. Differential Revision: https://reviews.llvm.org/D73934

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commit sha c1bcdb935a6b0f817109fde9b5e307fcaaab4b84

[mlir][ODS] Add documentation for the declarative assembly format. Summary: This details the structure of the format, it's requirements, and gives a few examples. Differential Revision: https://reviews.llvm.org/D73983

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commit sha f0fb09c33e390db16e47cc03a01d0e6f4578e0a7

[mlir] Print types to the OpAsmPrinter instead of the raw_ostream. This allows for reusing the internal state of the printer, which is more efficient and also allows for using type aliases

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commit sha abe6d1174df422915958c49c0367471c2de5df7a

[mlir] Emit a fatal error when the assembly format is invalid This revision makes sure that errors emitted outside of testing are treated as fatal errors. This avoids the current silent failures that occur when the format is invalid.

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commit sha 7ef37a5f9990eb51fc0ba8e09e9abc4bc8ef0e36

[mlir] Initial support for type constraints in the declarative assembly format Summary: This revision add support for accepting a few type constraints, e.g. AllTypesMatch, when inferring types for operands and results. This is used to remove the c++ parsers for several additional operations. Differential Revision: https://reviews.llvm.org/D73735

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commit sha fbba6395171d8644e859db8e4ca1ed662a0962bc

[mlir][ODS] Refactor BuildableType to use $_builder as part of the format Summary: Currently BuildableType is assumed to be preceded by a builder. This prevents constructing types that don't have a callable 'get' method with the builder. This revision reworks the format to be like attribute builders, i.e. by accepting $_builder within the format itself. Differential Revision: https://reviews.llvm.org/D73736

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commit sha 75c328179e0074eb0bdad7556ef430c0ffb81ca1

[mlir][DialectConversion] Remove invalid NDEBUG wrapper. The functions are used, but empty when NDEBUG is set.

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commit sha 4948b8b3cf485159da64fca81a9903610a830281

[mlir][NFC] Refactor DialectConversion debug logging Summary: This revision beefs up the debug logging within dialect conversion. Given the nature of multi-level legalization, and legalization in general, it is one of the harder pieces of infrastructure to debug. This revision adds nice formatting to make the output log easier to parse: ``` Legalizing operation : 'std.constant'(0x608000002420) { * Fold { } -> FAILURE : unable to fold * Pattern : 'std.constant -> ()' { } -> FAILURE : pattern failed to match * Pattern : 'std.constant -> ()' { } -> FAILURE : pattern failed to match * Pattern : 'std.constant -> (spv.constant)' { ** Insert : 'spv.constant'(0x608000002c20) ** Replace : 'std.constant'(0x608000002420) //===-------------------------------------------===// Legalizing operation : 'spv.constant'(0x608000002c20) { } -> SUCCESS : operation marked legal by the target //===-------------------------------------------===// } -> SUCCESS : pattern applied successfully } -> SUCCESS ``` Differential Revision: https://reviews.llvm.org/D73747

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commit sha b3a1d09c1c7a50069941021881a8174409d90975

[mlir] Add initial support for parsing a declarative operation assembly format Summary: This is the first revision in a series that adds support for declaratively specifying the asm format of an operation. This revision focuses solely on parsing the format. Future revisions will add support for generating the proper parser/printer, as well as transitioning the syntax definition of many existing operations. This was originally proposed here: https://llvm.discourse.group/t/rfc-declarative-op-assembly-format/340 Differential Revision: https://reviews.llvm.org/D73405

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commit sha 1c158d0f90919ba19b8749556ac3a60e9d99a312

[mlir] Add support for generating the parser/printer from the declarative operation format. Summary: This revision add support, and testing, for generating the parser and printer from the declarative operation format. Differential Revision: https://reviews.llvm.org/D73406

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commit sha 82170d5619987aac0de1f7cc62bdcdc8a68e783c

[mlir] Update various operations to declaratively specify their assembly format. Summary: This revision switches over many operations to use the declarative methods for defining the assembly specification. This updates operations in the NVVM, ROCDL, Standard, and VectorOps dialects. Differential Revision: https://reviews.llvm.org/D73407

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commit sha 528adb2e48035da1f0954d09236f7a63f79feab3

[mlir][NFC] Use declarative format for several operations in LLVM and Linalg dialects Differential Revision: https://reviews.llvm.org/D73503

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commit sha 389b12621041a03d693b3f369107df8f8dccf19e

[mlir][NFC] Update several SPIRV operations to use declarative parsers. Differential Revision: https://reviews.llvm.org/D73504

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commit sha 6b9e2be8ec322b631a91dca3c503b0850cdc0970

[mlir][NFC] Explicitly initialize dynamic legality when setting op action.

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commit sha 60b884208427f8cd317e8d40e64f113c6475c609

[mlir] Optimize OpResult use case for single result operations. Summary: Operation represents all of the uses of each result with one use list, so manipulating the use list of a specific result requires filtering the main use list. This revision adds an optimization for the case of single result operations to avoid this filtering. Differential Revision: https://reviews.llvm.org/D73430

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commit sha 57540c96bef9c568ac4984d171bc9797abf9b2f5

[mlir] Replace toy::DeadFunctionEliminationPass with symbolDCEPass. Summary: The dead function elimination pass in toy was a temporary stopgap until we had proper dead function elimination support in MLIR. Now that this functionality is available, this pass is no longer necessary. Differential Revision: https://reviews.llvm.org/D72483

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commit sha b276dec5b65dfb885bf661484b9eab1e719c5e47

[mlir] Add a DCE pass for dead symbols. Summary: This pass deletes all symbols that are found to be unreachable. This is done by computing the set of operations that are known to be live, propagating that liveness to other symbols, and then deleting all symbols that are not within this live set. Differential Revision: https://reviews.llvm.org/D72482

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commit sha ab9e5598cdc793890f514c2756866c53ad7971f3

[mlir] Refactor the implementation of Symbol use lists. Summary: This revision refactors the implementation of the symbol use-list functionality to be a bit cleaner, as well as easier to reason about. Aside from code cleanup, this revision updates the user contract to never recurse into operations if they define a symbol table. The current functionality, which does recurse, makes it difficult to examine the uses held by a symbol table itself. Moving forward users may provide a specific region to examine for uses instead. Differential Revision: https://reviews.llvm.org/D73427

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commit sha aff4ed73268d4930618b547bde21325bf8b662b7

[mlir][NFC] Update Operation::getResultTypes to use ArrayRef<Type> instead of iterator_range. Summary: The new internal representation of operation results now allows for accessing the result types to be more efficient. Changing the API to ArrayRef is more efficient and removes the need to explicitly materialize vectors in several places. Differential Revision: https://reviews.llvm.org/D73429

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commit sha ce674b131b66105ecd3918a11de4eb0205b50f99

[mlir] Add support for marking 'unknown' operations as dynamically legal. Summary: This allows for providing a default "catchall" legality check that is not dependent on specific operations or dialects. For example, this can be useful to check legality based on the specific types of operation operands or results. Differential Revision: https://reviews.llvm.org/D73379

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commit sha 8fb29d4a507371224ee06a039f1c01e242099967

[mlir] Replace AbstractOperation::classof with a ClassID instance. Summary: This field is currently not used by anything, and using a ClassID instance provides better support for more efficient classof. Reviewers: mehdi_amini, nicolasvasilache Reviewed By: mehdi_amini Subscribers: merge_guards_bot, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72822

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commit sha fa9dd8336bbd1167926f93fe2018d0c47839d5d6

[mlir] Refactor ModuleState into AsmState and expose it to users. Summary: This allows for users to cache printer state, which can be costly to recompute. Each of the IR print methods gain a new overload taking this new state class. Depends On D72293 Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D72294

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commit sha 20c6e0749461147df19a3b126d1a48106c63c351

[mlir] Enable printing of FuncOp in the generic form. Summary: This was previously disabled as FunctionType TypeAttrs could not be roundtripped in the IR. This has been fixed, so we can now generically print FuncOp. Depends On D72429 Reviewed By: jpienaar, mehdi_amini Differential Revision: https://reviews.llvm.org/D72642

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commit sha 1bd14ce39293df61888042916a7e43b9e502a4de

[mlir] Use double format when parsing bfloat16 hexadecimal values Summary: bfloat16 doesn't have a valid APFloat format, so we have to use double semantics when storing it. This change makes sure that hexadecimal values can be round-tripped properly given this fact. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D72667

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commit sha 03edd6d6a693e5bc7b0df488c4d4901cc55d3566

[mlir] NFC: Remove unused variable.

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commit sha 9b92e4fbdb5bc4fdd21702e0ce104dfcac6a54a7

[mlir] Add support for attaching a visibility to symbols. Summary: The visibility defines the structural reachability of the symbol within the IR. Symbols can define one of three visibilities: * Public The symbol \may be accessed from outside of the visible IR. We cannot assume that we can observe all of the uses of this symbol. * Private The symbol may only be referenced from within the operations in the current symbol table, via SymbolRefAttr. * Nested The symbol may be referenced by operations in symbol tables above the current symbol table, as long as each symbol table parent also defines a non-private symbol. This allows or referencing the symbol from outside of the defining symbol table, while retaining the ability for the compiler to see all uses. These properties help to reason about the properties of a symbol, and will be used in a follow up to implement a dce pass on dead symbols. A few examples of what this would look like in the IR are shown below: module @public_module { // This function can be accessed by 'live.user' func @nested_function() attributes { sym_visibility = "nested" } // This function cannot be accessed outside of 'public_module' func @private_function() attributes { sym_visibility = "private" } } // This function can only be accessed from within this module. func @private_function() attributes { sym_visibility = "private" } // This function may be referenced externally. func @public_function() "live.user"() {uses = [@public_module::@nested_function, @private_function, @public_function]} : () -> () Depends On D72043 Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D72044

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commit sha c7748404920b3674e79059cbbe73b6041a214444

[mlir] Update the CallGraph for nested symbol references, and simplify CallableOpInterface Summary: This enables tracking calls that cross symbol table boundaries. It also simplifies some of the implementation details of CallableOpInterface, i.e. there can only be one region within the callable operation. Depends On D72042 Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D72043

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commit sha 6fca03f0cae77c275870c4569bfeeb7ca0f561a6

[mlir] Update the use-list algorithms in SymbolTable to support nested references. Summary: This updates the use list algorithms to support querying from a specific symbol, allowing for the collection and detection of nested references. This works by walking the parent "symbol scopes" and applying the existing algorithm at each level. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D72042

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commit sha cb89c7e3f744c1fede60f7d1c43528654de676bd

[mlir] Remove unnecessary assert for single region. This was left over debugging.

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commit sha 4268e4f4b84b85266426e99050d31ec63f3ce8aa

[mlir] Change the syntax of AffineMapAttr and IntegerSetAttr to avoid conflicts with function types. Summary: The current syntax for AffineMapAttr and IntegerSetAttr conflict with function types, making it currently impossible to round-trip function types(and e.g. FuncOp) in the IR. This revision changes the syntax for the attributes by wrapping them in a keyword. AffineMapAttr is wrapped with `affine_map<>` and IntegerSetAttr is wrapped with `affine_set<>`. Reviewed By: nicolasvasilache, ftynse Differential Revision: https://reviews.llvm.org/D72429

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commit sha 2bdf33cc4c733342fc83081bc7410ac5e9a24f55

[mlir] NFC: Remove Value::operator* and Value::operator-> now that Value is properly value-typed. Summary: These were temporary methods used to simplify the transition. Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D72548

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commit sha 68c8b6c4cd117cc962155298f0e1d45056ecc001

[mlir] Use getDenseElementBitwidth instead of Type::getElementTypeBitWidth. Summary: Some data values have a different storage width than the corresponding MLIR type, e.g. bfloat is currently stored as a double. Reviewed By: nicolasvasilache Differential Revision: https://reviews.llvm.org/D72478

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commit sha fc3367dd5ed4698036c421b23cf4f52cf8aedcae

[mlir] NFC: Move the state for managing SSA value names out of OperationPrinter and into a new class SSANameState. Summary: This reduces the complexity of OperationPrinter and simplifies the code by quite a bit. The SSANameState is now held by ModuleState. This is in preparation for a future revision that molds ModuleState into something that can be used by users for caching the printer state, as well as for implementing printAsOperand style methods. Depends On D72292 Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D72293

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commit sha 659f7d463b3d677823fdcfddc37eea481078c514

[mlir] NFC: Move the state for managing aliases out of ModuleState and into a new class AliasState. Summary: This reduces the complexity of ModuleState and simplifies the code. A future revision will mold ModuleState into something that can be used by users for caching of printer state, as well as for implementing printAsOperand style methods. Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D72292

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Pull request review commenttensorflow/mlir

Add uitofp to the standard dialect.

 bool SIToFPOp::areCastCompatible(Type a, Type b) {   return a.isa<IntegerType>() && b.isa<FloatType>(); } +//===----------------------------------------------------------------------===//+// UIToFPOp+//===----------------------------------------------------------------------===//++// uitofp is applicable from integer types to float types.

Use /// for function comments.

ombre5733

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Pull request review commenttensorflow/mlir

Add uitofp to the standard dialect.

 bool SIToFPOp::areCastCompatible(Type a, Type b) {   return a.isa<IntegerType>() && b.isa<FloatType>(); } +//===----------------------------------------------------------------------===//

Keep the operations sorted to match .td file.

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Pull request review commenttensorflow/mlir

Add uitofp to the standard dialect.

 def TruncateIOp : Std_Op<"trunci", [NoSideEffect, SameOperandsAndResultShape]> {   }]; } +def UIToFPOp : CastOp<"uitofp">, Arguments<(ins AnyType:$in)> {

We should constrain the input to be an integer type, and the output to a floating point.

ombre5733

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Pull request review commenttensorflow/mlir

Add uitofp to the standard dialect.

 def TruncateIOp : Std_Op<"trunci", [NoSideEffect, SameOperandsAndResultShape]> {   }]; } +def UIToFPOp : CastOp<"uitofp">, Arguments<(ins AnyType:$in)> {+  let summary = "cast from unsigned integer type to floating-point";+  let description = [{+    Cast from a value interpreted as unsigned integer to the corresponding+    floating-point value. If the value cannot be exactly represented, it is+    rounded using the default rounding mode. Only scalars are currently+    supported.+  }];++  let extraClassDeclaration = [{+    /// Return true if `a` and `b` are valid operand and result pairs for+    /// the operation.+    static bool areCastCompatible(Type a, Type b);+  }];++  let hasFolder = 0;

Why is this set to 0?

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River Riddle

commit sha 0d9ca98c1a4676837e6e1f4ea9d9d1dea789b88c

[mlir] Fix indexed_accessor_range to properly forward the derived class. Summary: This fixes the return value of helper methods on the base range class. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D72127

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[mlir] Rewrite the internal representation of OpResult to be optimized for memory. Summary: This changes the implementation of OpResult to have some of the results be represented inline in Value, via a pointer int pair of Operation*+result number, and the rest being trailing objects on the main operation. The full details of the new representation is detailed in the proposal here: https://groups.google.com/a/tensorflow.org/g/mlir/c/XXzzKhqqF_0/m/v6bKb08WCgAJ The only difference between here and the above proposal is that we only steal 2-bits for the Value kind instead of 3. This means that we can only fit 2-results inline instead of 6. This allows for other users to steal the final bit for PointerUnion/etc. If necessary, we can always steal this bit back in the future to save more space if 3-6 results are common enough. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D72020

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Fix some corner cases missed by D71955 * replaceAllUsesWith may be supplied with a null value. * some compilers fail to implicitly convert single result operations to OpaqueValue, so add an explicit OpOperand::set(Value) method.

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commit sha 0d6ebb4f0dd7ca81bdfc2a210b1d5ef46e0c9587

[mlir] Refactor operation results to use a single use list for all results of the operation. Summary: A new class is added, IRMultiObjectWithUseList, that allows for representing an IR use list that holds multiple sub values(used in this case for OpResults). This class provides all of the same functionality as the base IRObjectWithUseList, but for specific sub-values. This saves a word per operation result and is a necessary step in optimizing the layout of operation results. For now the use list is placed on the operation itself, so zero-result operations grow by a word. When the work for optimizing layout is finished, this can be moved back to being a trailing object based on memory/runtime benchmarking. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D71955

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[mlir] Merge the successor operand count into BlockOperand. Summary: The successor operand counts are directly tied to block operands anyways, and this simplifies the trailing objects of Operation(i.e. one less computation to perform). Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D71949

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NFC: Rename printOptionValue to printValue to fix MSVC build. MSVC has trouble resolving the static 'printOptionValue' from the method on llvm::cl::opt/list. This change renames the static method to avoid this conflict.

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Artem Dergachev

commit sha 040c39d50fb9c60de9020caf86e1a1fccfd6f861

[analyzer] Fix false positive on introspection of a block's internal layout. When implementation of the block runtime is available, we should not warn that block layout fields are uninitialized simply because they're on the stack.

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Craig Topper

commit sha 28b573d2497e394d54d47778012887ab66d51f6f

[TargetLowering] Fix another potential FPE in expandFP_TO_UINT D53794 introduced code to perform the FP_TO_UINT expansion via FP_TO_SINT in a way that would never expose floating-point exceptions in the intermediate steps. Unfortunately, I just noticed there is still a way this can happen. As discussed in D53794, the compiler now generates this sequence: // Sel = Src < 0x8000000000000000 // Val = select Sel, Src, Src - 0x8000000000000000 // Ofs = select Sel, 0, 0x8000000000000000 // Result = fp_to_sint(Val) ^ Ofs The problem is with the Src - 0x8000000000000000 expression. As I mentioned in the original review, that expression can never overflow or underflow if the original value is in range for FP_TO_UINT. But I missed that we can get an Inexact exception in the case where Src is a very small positive value. (In this case the result of the sub is ignored, but that doesn't help.) Instead, I'd suggest to use the following sequence: // Sel = Src < 0x8000000000000000 // FltOfs = select Sel, 0, 0x8000000000000000 // IntOfs = select Sel, 0, 0x8000000000000000 // Result = fp_to_sint(Val - FltOfs) ^ IntOfs In the case where the value is already in range of FP_TO_SINT, we now simply compute Val - 0, which now definitely cannot trap (unless Val is a NaN in which case we'd want to trap anyway). In the case where the value is not in range of FP_TO_SINT, but still in range of FP_TO_UINT, the sub can never be inexact, as Val is between 2^(n-1) and (2^n)-1, i.e. always has the 2^(n-1) bit set, and the sub is always simply clearing that bit. There is a slight complication in the case where Val is a constant, so we know at compile time whether Sel is true or false. In that scenario, the old code would automatically optimize the sub away, while this no longer happens with the new code. Instead, I've added extra code to check for this case and then just fall back to FP_TO_SINT directly. (This seems to catch even slightly more cases.) Original version of the patch by Ulrich Weigand. X86 changes added by Craig Topper Differential Revision: https://reviews.llvm.org/D67105

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Nico Weber

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wrap an rst file to 80 cols, to cycle bots

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Alex Lorenz

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[ObjC] Make sure that the implicit arguments for direct methods have been setup This commit sets the Self and Imp declarations for ObjC method declarations, in addition to the definitions. It also fixes a bunch of code in clang that had wrong assumptions about when getSelfDecl() would be set: - CGDebugInfo::getObjCMethodName and AnalysisConsumer::getFunctionName would assume that it was set for method declarations part of a protocol, which they never were, and that self would be a Class type, which it isn't as it is id for a protocol. Also use the Canonical Decl to index the set of Direct methods so that when calls and implementations interleave, the same llvm::Function is used and the same symbol name emitted. Radar-Id: rdar://problem/57661767 Patch by: Pierre Habouzit Differential Revision: https://reviews.llvm.org/D71091

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Amara Emerson

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[X86] Fix prolog/epilog mismatch for stack protectors on win32-macho. The xor'ing behaviour is only used for msvc/crt environments, when we're targeting macho the guard load code doesn't know about the xor in the epilog. Disable xor'ing when targeting win32-macho to be consistent. Differential Revision: https://reviews.llvm.org/D71095

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Reid Kleckner

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[MC] Rewrite tablegen for printInstrAlias to comiple faster, NFC Before this change, the *InstPrinter.cpp files of each target where some of the slowest objects to compile in all of LLVM. See this snippet produced by ClangBuildAnalyzer: https://reviews.llvm.org/P8171$96 Search for "InstPrinter", and see that it shows up in a few places. Tablegen was emitting a large switch containing a sequence of operand checks, each of which created many conditions and many BBs. Register allocation and jump threading both did not scale well with such a large repetitive sequence of basic blocks. So, this change essentially turns those control flow structures into data. The previous structure looked like: switch (Opc) { case TGT::ADD: // check alias 1 if (MI->getOperandCount() == N && // check num opnds MI->getOperand(0).isReg() && // check opnd 0 ... MI->getOperand(1).isImm() && // check opnd 1 AsmString = "foo"; break; } // check alias 2 if (...) ... return false; The new structure looks like: OpToPatterns: Sorted table of opcodes mapping to pattern indices. \-> Patterns: List of patterns. Previous table points to subrange of patterns to match. \-> Conds: The if conditions above encoded as a kind and 32-bit value. See MCInstPrinter.cpp for the details of how the new data structures are interpreted. Here are some before and after metrics. Time to compile AArch64InstPrinter.cpp: 0m29.062s vs. 0m2.203s size of the obj: 3.9M vs. 676K size of clang.exe: 97M vs. 96M I have not benchmarked disassembly performance, but typically disassemblers are bottlenecked on IO and string processing, not alias matching, so I'm not sure it's interesting enough to be worth doing. Reviewers: RKSimon, andreadb, xbolva00, craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D70650

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Sam Clegg

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[WebAssebmly][MC] Support .import_name/.import_field asm directives Convert the MC test to use asm rather than bitcode. This is a precursor to https://reviews.llvm.org/D70520. Differential Revision: https://reviews.llvm.org/D70877

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Stephen Kelly

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Make it possible control matcher traversal kind with ASTContext Summary: This will eventually allow traversal of an AST while ignoring invisible AST nodes. Currently it depends on the available enum values for TraversalKinds. That can be extended to ignore all invisible nodes in the future. Reviewers: klimek, aaron.ballman Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D61837

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Don Hinton

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[CommandLine] Add callbacks to Options Summary: Add a new cl::callback attribute to Option. This attribute specifies a callback function that is called when an option is seen, and can be used to set other options, as in option A implies option B. If the option is a `cl::list`, and `cl::CommaSeparated` is also specified, the callback will fire once for each value. This could be used to validate combinations or selectively set other options. Reviewers: beanz, thomasfinch, MaskRay, thopre, serge-sans-paille Reviewed By: beanz Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70620

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Reid Kleckner

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Remove Expr.h include from ASTContext.h, NFC ASTContext.h is popular, prune its includes. Expr.h brings in Attr.h, which is also expensive. Move BlockVarCopyInit to Expr.h to accomplish this.

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Craig Topper

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[Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize. The validateOutputSize and validateInputSize need to check whether AVX or AVX512 are enabled. But this can be affected by the target attribute so we need to factor that in. This patch copies some of the code from CodeGen to create an appropriate feature map that we can pass to the function. Probably need some refactoring here to share more code with Codegen. Is there a good place to do that? Also need to support the cpu_specific attribute as well. Differential Revision: https://reviews.llvm.org/D68627

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Stephen Kelly

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Use ASTDumper to dump the AST from clang-query Summary: This way, the output is not limited by the various API differences between the dump() member functions. For example, all dumps are now in color, while that used to be the case only for Decls and Stmts, but not Types. Additionally, while DynTypedNode::dump (which was used up to now) was limited to dumping only Decls, Stmts and Types, this makes clang-query support everything ASTNodeTraverser supports. Reviewers: aaron.ballman Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62056

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Reid Kleckner

commit sha eff08f40976e177923fe95759917e59375458f71

Revert "[Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize." This reverts commit e1578fd2b79fe5af5f80c0c166a8abd0f816c022. It introduces a dependency on Attr.h which I am removing from ASTContext.h.

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Peter Collingbourne

commit sha 3131249204bcb85e506332ea07a3101b7f656fce

gn build: Change scudo's list of supported platforms to a whitelist. Scudo only supports building for android/linux/fuchsia, so require target_os to be one of linux/fuchsia to do a stage2_unix scudo build. Android is already covered by the stage2_android* toolchains below. Differential Revision: https://reviews.llvm.org/D71131

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Stephen Kelly

commit sha 2e8dc8590d8b412a131b127e7aa4aad0d7fc7fa0

Add matchDynamic convenience functions Summary: These correspond to the existing match() free functions. Reviewers: aaron.ballman Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D54406

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Jonas Devlieghere

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[lldb/Reproducer] Disable test on Windows to unblock the bot. http://lab.llvm.org:8011/builders/lldb-x64-windows-ninja

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Amara Emerson

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[AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates. Only implemented for the type combinations already supported for G_SHL. Differential Revision: https://reviews.llvm.org/D71153

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Richard Smith

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[c++20] Determine whether a defaulted comparison should be deleted or constexpr.

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Sterling Augustine

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Move variable only used in an assert into the assert itself. This prevents unused variable warnings from breaking the build.

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Amara Emerson

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[AArch64][GlobalISel] Add missing default statement to a switch in the selector.

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River Riddle

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Tablegen: Remove the error for duplicate include files. This was originally added a while(7 years) ago when including multiple files was basically always an error. Tablgen now has preprocessor support, which allows for building nice c/c++ style include guards. With the current error being reported, we need to double guard when including files: * In user of MyFile.td ifndef MYFILE_TD include MyFile.td endif * In MyFile.td ifndef MYFILE_TD define MYFILE_TD ... endif

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River Riddle

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Revert "Tablegen: Remove the error for duplicate include files." This reverts commit 6c022949fe450ddc8075d2cb2f3e4de46eed24bf.

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pull request commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

(Github won't let me respond to an outdated conversation, which is annoying).

It's not clear to me how to group block argument names What I had in mind for "grouping" is just how the interface with the 'setValueName' function works, not how the IR is actually printed. If we "grouped" block arguments, it would just mean that each argument should be prefixed with that name. Though, given that block arguments function a bit differently than operation results, it should be fine to have the behavior be slightly different. This difference should be clearly marked in a comment on the method though.

I haven’t found a need for this feature. Could we do this as a follow up PR?

SGTM

flaub

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Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 void OperationPrinter::numberValuesInRegion(Region &region) { }  void OperationPrinter::numberValuesInBlock(Block &block) {+  auto setArgNameFn = [&](Value *arg, StringRef name) {+    assert(!valueIDs.count(arg) && "arg numbered multiple times");+    assert(cast<BlockArgument>(arg)->getOwner() == &block &&+           "arg not defined in 'block'");+    setValueName(arg, name);+  };+   bool isEntryBlock = block.isEntryBlock();+  if (isEntryBlock && state) {+    if (auto *op = block.getParentOp()) {+      if (auto dialectAsmInterface = state->getOpAsmInterface(op->getDialect()))+        dialectAsmInterface->getAsmBlockArgumentNames(&block, setArgNameFn);+    }+  }    // Number the block arguments. We give entry block arguments a special name   // 'arg'.-  SmallString<32> specialNameBuffer(isEntryBlock ? "arg" : "");-  llvm::raw_svector_ostream specialName(specialNameBuffer);-  for (auto *arg : block.getArguments()) {-    if (isEntryBlock) {-      specialNameBuffer.resize(strlen("arg"));+  for (auto arg : block.getArguments()) {+    if (valueIDs.count(arg))+      continue;+    SmallString<32> specialNameBuffer(isEntryBlock ? "arg" : "");+    llvm::raw_svector_ostream specialName(specialNameBuffer);

Seems like this loop can just be reverted modulo the if (valueIds.count(...)) check at the beginning.

flaub

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Pull request review commenttensorflow/mlir

Introduce prefetch op: affine -> std -> llvm intrinsic

 OpFoldResult MulIOp::fold(ArrayRef<Attribute> operands) {                                         [](APInt a, APInt b) { return a * b; }); } +//===----------------------------------------------------------------------===//+// PrefetchOp+//===----------------------------------------------------------------------===//++static void print(OpAsmPrinter &p, PrefetchOp op) {+  p << PrefetchOp::getOperationName() << " " << *op.memref() << '[';+  p.printOperands(op.indices());+  p << ']' << ", " << (op.isWrite() ? "write" : "read");+  p << ", locality<" << op.localityHint();+  p << ">, " << (op.isDataCache() ? "data" : "instr");+  p.printOptionalAttrDict(+      op.getAttrs(),+      /*elidedAttrs=*/{"localityHint", "isWrite", "isDataCache"});+  p << " : " << op.getMemRefType();+}++static ParseResult parsePrefetchOp(OpAsmParser &parser,+                                   OperationState &result) {+  OpAsmParser::OperandType memrefInfo;+  SmallVector<OpAsmParser::OperandType, 4> indexInfo;+  IntegerAttr localityHint;+  MemRefType type;+  StringRef readOrWrite, cacheType;++  auto indexTy = parser.getBuilder().getIndexType();+  auto i32Type = parser.getBuilder().getIntegerType(32);+  if (parser.parseOperand(memrefInfo) ||+      parser.parseOperandList(indexInfo, OpAsmParser::Delimiter::Square) ||+      parser.parseComma() || parser.parseKeyword(&readOrWrite) ||+      parser.parseComma() || parser.parseKeyword("locality") ||+      parser.parseLess() ||+      parser.parseAttribute(localityHint, i32Type, "localityHint",+                            result.attributes) ||+      parser.parseGreater() || parser.parseComma() ||+      parser.parseKeyword(&cacheType) || parser.parseColonType(type) ||+      parser.resolveOperand(memrefInfo, type, result.operands) ||+      parser.resolveOperands(indexInfo, indexTy, result.operands))+    return failure();++  if (!readOrWrite.equals("read") && !readOrWrite.equals("write"))+    return parser.emitError(parser.getNameLoc(),+                            "rw specifier has to be 'read' or 'write'");+  result.addAttribute(+      PrefetchOp::getIsWriteAttrName(),+      parser.getBuilder().getBoolAttr(readOrWrite.equals("write")));++  if (!cacheType.equals("data") && !cacheType.equals("instr"))+    return parser.emitError(parser.getNameLoc(),+                            "cache type has to be 'data' or 'instr'");++  result.addAttribute(+      PrefetchOp::getIsDataCacheAttrName(),+      parser.getBuilder().getBoolAttr(cacheType.equals("data")));++  return success();+}++static LogicalResult verify(PrefetchOp op) {+  if (op.getNumOperands() != 1 + op.getMemRefType().getRank())+    return op.emitOpError("too few indices");

No coverage here.

bondhugula

comment created time in 2 months

Pull request review commenttensorflow/mlir

Introduce prefetch op: affine -> std -> llvm intrinsic

 OpFoldResult AffineMinOp::fold(ArrayRef<Attribute> operands) {   return results[minIndex]; } +//===----------------------------------------------------------------------===//+// AffinePrefetchOp+//===----------------------------------------------------------------------===//++//+// affine.prefetch %0[%i, %j + 5], read, locality<3>, data : memref<400x400xi32>+//+static ParseResult parseAffinePrefetchOp(OpAsmParser &parser,+                                         OperationState &result) {+  auto &builder = parser.getBuilder();+  auto indexTy = builder.getIndexType();++  MemRefType type;+  OpAsmParser::OperandType memrefInfo;+  IntegerAttr hintInfo;+  auto i32Type = parser.getBuilder().getIntegerType(32);+  StringRef readOrWrite, cacheType;++  AffineMapAttr mapAttr;+  SmallVector<OpAsmParser::OperandType, 1> mapOperands;+  if (parser.parseOperand(memrefInfo) ||+      parser.parseAffineMapOfSSAIds(mapOperands, mapAttr,+                                    AffinePrefetchOp::getMapAttrName(),+                                    result.attributes) ||+      parser.parseComma() || parser.parseKeyword(&readOrWrite) ||+      parser.parseComma() || parser.parseKeyword("locality") ||+      parser.parseLess() ||+      parser.parseAttribute(hintInfo, i32Type,+                            AffinePrefetchOp::getLocalityHintAttrName(),+                            result.attributes) ||+      parser.parseGreater() || parser.parseComma() ||+      parser.parseKeyword(&cacheType) ||+      parser.parseOptionalAttrDict(result.attributes) ||+      parser.parseColonType(type) ||+      parser.resolveOperand(memrefInfo, type, result.operands) ||+      parser.resolveOperands(mapOperands, indexTy, result.operands))+    return failure();++  if (!readOrWrite.equals("read") && !readOrWrite.equals("write"))+    return parser.emitError(parser.getNameLoc(),+                            "rw specifier has to be 'read' or 'write'");+  result.addAttribute(+      AffinePrefetchOp::getIsWriteAttrName(),+      parser.getBuilder().getBoolAttr(readOrWrite.equals("write")));++  if (!cacheType.equals("data") && !cacheType.equals("instr"))+    return parser.emitError(parser.getNameLoc(),+                            "cache type has to be 'data' or 'instr'");++  result.addAttribute(+      AffinePrefetchOp::getIsDataCacheAttrName(),+      parser.getBuilder().getBoolAttr(cacheType.equals("data")));++  return success();+}++void print(OpAsmPrinter &p, AffinePrefetchOp op) {+  p << AffinePrefetchOp::getOperationName() << " " << *op.memref() << '[';+  AffineMapAttr mapAttr = op.getAttrOfType<AffineMapAttr>(op.getMapAttrName());+  if (mapAttr) {+    SmallVector<Value *, 2> operands(op.getMapOperands());+    p.printAffineMapOfSSAIds(mapAttr, operands);+  }+  p << ']' << ", " << (op.isWrite() ? "write" : "read") << ", "+    << "locality<" << op.localityHint() << ">, "+    << (op.isDataCache() ? "data" : "instr");+  p.printOptionalAttrDict(+      op.getAttrs(),+      /*elidedAttrs=*/{op.getMapAttrName(), op.getLocalityHintAttrName(),+                       op.getIsDataCacheAttrName(), op.getIsWriteAttrName()});+  p << " : " << op.getMemRefType();+}++LogicalResult verify(AffinePrefetchOp op) {+  auto mapAttr = op.getAttrOfType<AffineMapAttr>(op.getMapAttrName());+  if (mapAttr) {+    AffineMap map = mapAttr.getValue();+    if (map.getNumResults() != op.getMemRefType().getRank())+      return op.emitOpError("affine.prefetch affine map num results must equal"

Missing coverage on all of these failure cases

bondhugula

comment created time in 2 months

Pull request review commenttensorflow/mlir

Introduce prefetch op: affine -> std -> llvm intrinsic

 void SimplifyAffineOp<AffineLoadOp>::replaceAffineOp(                                             mapOperands); } template <>+void SimplifyAffineOp<AffinePrefetchOp>::replaceAffineOp(+    PatternRewriter &rewriter, AffinePrefetchOp prefetch, AffineMap map,+    ArrayRef<Value *> mapOperands) const {+  rewriter.replaceOpWithNewOp<AffinePrefetchOp>(

This isn't covered by a test case.

bondhugula

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 struct TestOpAsmInterface : public OpAsmDialectInterface {     if (auto asmOp = dyn_cast<AsmDialectInterfaceOp>(op))       setNameFn(asmOp, "result");   }++  void getAsmBlockArgumentNames(Block *block,+                                OpAsmSetValueNameFn setNameFn) const final {+    auto op = block->getParentOp();+    if (auto arrayAttr = op->getAttrOfType<ArrayAttr>("arg_names")) {+      auto args = block->getArguments();+      for (unsigned i = 0; i < std::min(arrayAttr.size(), args.size()); i++) {

This is part of the MLIR(LLVM) coding standards: https://llvm.org/docs/CodingStandards.html

flaub

comment created time in 2 months

pull request commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

Coding standards apply across the entire codebase, the test dialect is no excuse to be inefficient/inconsistent.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 struct TestOpAsmInterface : public OpAsmDialectInterface {     if (auto asmOp = dyn_cast<AsmDialectInterfaceOp>(op))       setNameFn(asmOp, "result");   }++  void getAsmBlockArgumentNames(Block *block,+                                OpAsmSetValueNameFn setNameFn) const final {+    auto op = block->getParentOp();+    if (auto arrayAttr = op->getAttrOfType<ArrayAttr>("arg_names")) {

Same as the rest.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 struct TestOpAsmInterface : public OpAsmDialectInterface {     if (auto asmOp = dyn_cast<AsmDialectInterfaceOp>(op))       setNameFn(asmOp, "result");   }++  void getAsmBlockArgumentNames(Block *block,+                                OpAsmSetValueNameFn setNameFn) const final {+    auto op = block->getParentOp();+    if (auto arrayAttr = op->getAttrOfType<ArrayAttr>("arg_names")) {+      auto args = block->getArguments();+      for (unsigned i = 0; i < std::min(arrayAttr.size(), args.size()); i++) {+        if (auto strAttr = arrayAttr.getValue()[i].dyn_cast<StringAttr>()) {

Drop trivial braces.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 struct TestOpAsmInterface : public OpAsmDialectInterface {     if (auto asmOp = dyn_cast<AsmDialectInterfaceOp>(op))       setNameFn(asmOp, "result");   }++  void getAsmBlockArgumentNames(Block *block,+                                OpAsmSetValueNameFn setNameFn) const final {+    auto op = block->getParentOp();+    if (auto arrayAttr = op->getAttrOfType<ArrayAttr>("arg_names")) {

Prefer early exit:

auto arrayAttr = ...; if (!arrayAttr) return;

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 void OperationPrinter::numberValuesInRegion(Region &region) { }  void OperationPrinter::numberValuesInBlock(Block &block) {+  auto setArgNameFn = [&](Value *arg, StringRef name) {+    assert(!valueIDs.count(arg) && "arg numbered multiple times");+    assert(cast<BlockArgument>(arg)->getOwner() == &block &&+           "arg not defined in 'block'");+    setValueName(arg, name);+  };+   bool isEntryBlock = block.isEntryBlock();+  if (isEntryBlock && state) {+    if (auto *op = block.getParentOp()) {+      if (auto dialectAsmInterface = state->getOpAsmInterface(op->getDialect()))+        dialectAsmInterface->getAsmBlockArgumentNames(&block, setArgNameFn);+    }+  }    // Number the block arguments. We give entry block arguments a special name   // 'arg'.-  SmallString<32> specialNameBuffer(isEntryBlock ? "arg" : "");-  llvm::raw_svector_ostream specialName(specialNameBuffer);-  for (auto *arg : block.getArguments()) {-    if (isEntryBlock) {-      specialNameBuffer.resize(strlen("arg"));+  for (auto arg : block.getArguments()) {+    SmallString<32> specialNameBuffer(isEntryBlock ? "arg" : "");+    llvm::raw_svector_ostream specialName(specialNameBuffer);+    if (isEntryBlock)       specialName << nextArgumentID++;-    }-    setValueName(arg, specialName.str());+    if (!valueIDs.count(arg))

This check should be hoisted to the top of the loop:

for (BlockArgument *arg : block.getArguments()) { if (!...) continue;

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 struct TestOpAsmInterface : public OpAsmDialectInterface {     if (auto asmOp = dyn_cast<AsmDialectInterfaceOp>(op))       setNameFn(asmOp, "result");   }++  void getAsmBlockArgumentNames(Block *block,+                                OpAsmSetValueNameFn setNameFn) const final {+    auto op = block->getParentOp();+    if (auto arrayAttr = op->getAttrOfType<ArrayAttr>("arg_names")) {+      auto args = block->getArguments();+      for (unsigned i = 0; i < std::min(arrayAttr.size(), args.size()); i++) {

Cache the end iterator to avoid recomputation, and prefer preincrement

e = std::min(...); i != e; ++i

flaub

comment created time in 2 months

pull request commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

(Github won't let me respond to an outdated conversation, which is annoying).

It's not clear to me how to group block argument names What I had in mind for "grouping" is just how the interface with the 'setValueName' function works, not how the IR is actually printed. If we "grouped" block arguments, it would just mean that each argument should be prefixed with that name. Though, given that block arguments function a bit differently than operation results, it should be fine to have the behavior be slightly different. This difference should be clearly marked in a comment on the method though.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 void OperationPrinter::numberValuesInBlock(Block &block) {    // Number the block arguments. We give entry block arguments a special name   // 'arg'.-  SmallString<32> specialNameBuffer(isEntryBlock ? "arg" : "");-  llvm::raw_svector_ostream specialName(specialNameBuffer);+  const OpAsmDialectInterface *interface = nullptr;+  if (isEntryBlock && state) {+    if (auto *op = block.getParentOp()) {

Drop trivial braces.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 class OpAsmDialectInterface   /// OpAsmInterface.td#getAsmResultNames for usage details and documentation.   virtual void getAsmResultNames(Operation *op,                                  OpAsmSetValueNameFn setNameFn) const {}++  /// Get a special name to use when printing the entry block arguments of the+  /// region contained by an operation in this dialect.  The desired name should+  /// be streamed into 'os'.  If the result is empty, the default name will be+  /// used.+  virtual void getRegionArgumentName(BlockArgument *arg,+                                     raw_ostream &os) const {}

It would also be nice to add a hook to the OpAsmOpInterface, but that requires support for default implementations which is something I need to add. So I can do that as a follow up.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 class OpAsmParser {   virtual ParseResult parseColonType(Type &result) = 0;    /// Parse a colon followed by a type of a specific kind, e.g. a FunctionType.-  template <typename TypeType> ParseResult parseColonType(TypeType &result) {+  template <typename TypeType>+  ParseResult parseColonType(TypeType &result) {

This seems like an unrelated format change, likely caused by a different version of clang-format.

flaub

comment created time in 2 months

Pull request review commenttensorflow/mlir

Allow dialect to create friendly names for region arguments

 class OpAsmDialectInterface   /// OpAsmInterface.td#getAsmResultNames for usage details and documentation.   virtual void getAsmResultNames(Operation *op,                                  OpAsmSetValueNameFn setNameFn) const {}++  /// Get a special name to use when printing the entry block arguments of the+  /// region contained by an operation in this dialect.  The desired name should+  /// be streamed into 'os'.  If the result is empty, the default name will be+  /// used.+  virtual void getRegionArgumentName(BlockArgument *arg,+                                     raw_ostream &os) const {}

Can we set this up with the same structure as the result names? i.e. allow groups of names. That would make things more consistent and extensible.

flaub

comment created time in 2 months

pull request commenttensorflow/mlir

Allow dialect to create friendly names for block arguments

Internally at google we maintain both separately+simultaneously. If it helps your team, the TensorFlow copy of the MLIR BUILD files can be viewed at: https://github.com/tensorflow/tensorflow/blob/master/third_party/mlir/BUILD

jbruestle

comment created time in 2 months

Pull request review commenttensorflow/mlir

Add integer bit-shift operations to the standard dialect.

 func @args_ret_affine_apply(index, index) -> (index, index) { }  //===---------------------------------------------------------------------===//-// Test lowering of Euclidean (floor) division, ceil division and modulo+// Test lowering of Euclidean (floor) divi_signedion, ceil divi_signedion and modulo

Same here and a few other I believe.

ombre5733

comment created time in 2 months

Pull request review commenttensorflow/mlir

Add integer bit-shift operations to the standard dialect.

 func @mulf_splat_tensor() -> tensor<4xf32> {  // ----- -// CHECK-LABEL: func @simple_divis-func @simple_divis() -> (i32, i32, i32) {+// CHECK-LABEL: func @simple_divi_signed+func @simple_divi_signed() -> (i32, i32, i32) {   // CHECK-DAG: [[C0:%.+]] = constant 0   %z = constant 0 : i32   // CHECK-DAG: [[C6:%.+]] = constant 6   %0 = constant 6 : i32   %1 = constant 2 : i32    // CHECK-NEXT: [[C3:%.+]] = constant 3 : i32-  %2 = divis %0, %1 : i32+  %2 = divi_signed %0, %1 : i32    %3 = constant -2 : i32    // CHECK-NEXT: [[CM3:%.+]] = constant -3 : i32-  %4 = divis %0, %3 : i32+  %4 = divi_signed %0, %3 : i32 -  // CHECK-NEXT: [[XZ:%.+]] = divis [[C6]], [[C0]]-  %5 = divis %0, %z : i32+  // CHECK-NEXT: [[XZ:%.+]] = divi_signed [[C6]], [[C0]]+  %5 = divi_signed %0, %z : i32    // CHECK-NEXT: return [[C3]], [[CM3]], [[XZ]]   return %2, %4, %5 : i32, i32, i32 }  // ----- -// CHECK-LABEL: func @divis_splat_tensor-func @divis_splat_tensor() -> (tensor<4xi32>, tensor<4xi32>, tensor<4xi32>) {+// CHECK-LABEL: func @divi_signed_splat_tensor+func @divi_signed_splat_tensor() -> (tensor<4xi32>, tensor<4xi32>, tensor<4xi32>) {   // CHECK-DAG: [[C0:%.+]] = constant dense<0>   %z = constant dense<0> : tensor<4xi32>   // CHECK-DAG: [[C6:%.+]] = constant dense<6>   %0 = constant dense<6> : tensor<4xi32>   %1 = constant dense<2> : tensor<4xi32>    // CHECK-NEXT: [[C3:%.+]] = constant dense<3> : tensor<4xi32>-  %2 = divis %0, %1 : tensor<4xi32>+  %2 = divi_signed %0, %1 : tensor<4xi32>    %3 = constant dense<-2> : tensor<4xi32>    // CHECK-NEXT: [[CM3:%.+]] = constant dense<-3> : tensor<4xi32>-  %4 = divis %0, %3 : tensor<4xi32>+  %4 = divi_signed %0, %3 : tensor<4xi32> -  // CHECK-NEXT: [[XZ:%.+]] = divis [[C6]], [[C0]]-  %5 = divis %0, %z : tensor<4xi32>+  // CHECK-NEXT: [[XZ:%.+]] = divi_signed [[C6]], [[C0]]+  %5 = divi_signed %0, %z : tensor<4xi32>    // CHECK-NEXT: return [[C3]], [[CM3]], [[XZ]]   return %2, %4, %5 : tensor<4xi32>, tensor<4xi32>, tensor<4xi32> }  // ----- -// CHECK-LABEL: func @simple_diviu-func @simple_diviu() -> (i32, i32, i32) {+// CHECK-LABEL: func @simple_divi_unsigned+func @simple_divi_unsigned() -> (i32, i32, i32) {   %z = constant 0 : i32   // CHECK-DAG: [[C6:%.+]] = constant 6   %0 = constant 6 : i32   %1 = constant 2 : i32    // CHECK-DAG: [[C3:%.+]] = constant 3 : i32-  %2 = diviu %0, %1 : i32+  %2 = divi_unsigned %0, %1 : i32    %3 = constant -2 : i32 -  // Unsigned division interprets -2 as 2^32-2, so the result is 0.+  // Unsigned divi_signedion interprets -2 as 2^32-2, so the result is 0.

accidental change

ombre5733

comment created time in 2 months

Pull request review commenttensorflow/mlir

Add integer bit-shift operations to the standard dialect.

 func @simple_diviu() -> (i32, i32, i32) {  // ----- -// CHECK-LABEL: func @diviu_splat_tensor-func @diviu_splat_tensor() -> (tensor<4xi32>, tensor<4xi32>, tensor<4xi32>) {+// CHECK-LABEL: func @divi_unsigned_splat_tensor+func @divi_unsigned_splat_tensor() -> (tensor<4xi32>, tensor<4xi32>, tensor<4xi32>) {   %z = constant dense<0> : tensor<4xi32>   // CHECK-DAG: [[C6:%.+]] = constant dense<6>   %0 = constant dense<6> : tensor<4xi32>   %1 = constant dense<2> : tensor<4xi32>    // CHECK-DAG: [[C3:%.+]] = constant dense<3> : tensor<4xi32>-  %2 = diviu %0, %1 : tensor<4xi32>+  %2 = divi_unsigned %0, %1 : tensor<4xi32>    %3 = constant dense<-2> : tensor<4xi32> -  // Unsigned division interprets -2 as 2^32-2, so the result is 0.+  // Unsigned divi_signedion interprets -2 as 2^32-2, so the result is 0.

accidental changes?

ombre5733

comment created time in 2 months

issue closedtensorflow/mlir

Building error,"mlir/IR/OpBase.td"has a problem

[46/450] Building AffineOps.cpp.inc... FAILED: projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.cpp.inc cd /home/sun/llvm-project/build && /home/sun/llvm-project/build/bin/mlir-tblgen -gen-op-defs -I/home/sun/llvm-project/llvm/projects/mlir/include -I/home/sun/llvm-project/build/projects/mlir/include -I /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps -I /home/sun/llvm-project/llvm/include /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td --write-if-changed -o projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.cpp.inc -d projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.cpp.inc.d /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td:26:9: error: File '/home/sun/llvm-project/llvm/projects/mlir/include/mlir/IR/OpBase.td' has already been included. include "mlir/IR/OpBase.td" ^ Included from /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td:25: /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOpsBase.td:25:9: note: previously included here include "mlir/IR/OpBase.td" ^ /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td:26:9: error: Unexpected input at top level include "mlir/IR/OpBase.td" ^ [47/450] Building AffineOps.h.inc... FAILED: projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.h.inc cd /home/sun/llvm-project/build && /home/sun/llvm-project/build/bin/mlir-tblgen -gen-op-decls -I/home/sun/llvm-project/llvm/projects/mlir/include -I/home/sun/llvm-project/build/projects/mlir/include -I /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps -I /home/sun/llvm-project/llvm/include /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td --write-if-changed -o projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.h.inc -d projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.h.inc.d /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td:26:9: error: File '/home/sun/llvm-project/llvm/projects/mlir/include/mlir/IR/OpBase.td' has already been included. include "mlir/IR/OpBase.td" ^ Included from /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td:25: /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOpsBase.td:25:9: note: previously included here include "mlir/IR/OpBase.td" ^ /home/sun/llvm-project/llvm/projects/mlir/include/mlir/Dialect/AffineOps/AffineOps.td:26:9: error: Unexpected input at top level include "mlir/IR/OpBase.td"

closed time in 2 months

MingliSun

issue commenttensorflow/mlir

Building error,"mlir/IR/OpBase.td"has a problem

Closing this as it seems you have a separate issue now.

MingliSun

comment created time in 2 months

pull request commenttensorflow/mlir

Fix warning with struct forward declared as class

Seem like @nicolasvasilache submitted a fix as well: https://github.com/tensorflow/mlir/commit/0f79da8aaebd8b9605ee28762299b49b21630147

thewilsonator

comment created time in 2 months

pull request commenttensorflow/mlir

Implement removeOpIfDeadResults in PatternRewriter

Sorry for the delay. I may be biased, but I say we just remove it until there is a clear story in how it fits in with the rest of the infra.

dcaballe

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Expose subview promotion as a declarative pattern

 mlir::linalg::permuteGenericLinalgOp(PatternRewriter &rewriter, Operation *op,   linOp.clone(rewriter, linOp.getLoc(), op->getOperands());   return success(); }++LogicalResult mlir::linalg::linalgOpPromoteSubviews(PatternRewriter &rewriter,+                                                    Operation *op) {+  LinalgOp linOp = dyn_cast<LinalgOp>(op);+  SetVector<Value *> subViews;+  for (auto it : linOp.getInputsAndOutputs())+    if (auto sv = dyn_cast_or_null<SubViewOp>(it->getDefiningOp()))+      subViews.insert(sv);+  if (!subViews.empty()) {+    auto resOp = promoteSubViewOperands(rewriter, linOp, subViews);+    if (!resOp)

return success(resOp); ?

tetuante

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Expose subview promotion as a declarative pattern

 static void promoteSubViewOperands(LinalgOp op, SetVector<Value *> subViews,   // extra scalars etc.   auto operands = getAssumedNonViewOperands(op);   opViews.append(operands.begin(), operands.end());-  op.clone(b, op.getLoc(), opViews);+  LinalgOp res = op.clone(b, op.getLoc(), opViews);    // 3. Emit write-back for the promoted output views: copy the partial view.   for (auto viewAndPartialLocalView : writebackViews) {     // Note: use the old op to determine whether the operand view is an output.     bool isOutput =-        op.getIndexOfOutput(viewAndPartialLocalView.first).hasValue();+        res.getIndexOfOutput(viewAndPartialLocalView.first).hasValue();     if (isOutput)       copy(viewAndPartialLocalView.second, viewAndPartialLocalView.first);   }    // 4. Dealloc local buffers.   for (const auto &pi : promotedBufferAndViews)     dealloc(pi.buffer);++  return res; // std::move?

Drop the comment here.

tetuante

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Expose subview promotion as a declarative pattern

 LogicalResult vectorizeGenericOp(PatternRewriter &rewriter, Operation *op); LogicalResult permuteGenericLinalgOp(PatternRewriter &rewriter, Operation *op,                                      ArrayRef<unsigned> permutation,                                      StringRef linalgMarker);++// Promote std.subviews feeding linalg operations

// -> ///

tetuante

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Expose subview promotion as a declarative pattern

 class AffineMapDomainHasDim<int n> : CPred<[{   $0.getAttrOfType<ArrayAttr>(getIndexingMapsAttrName()).getValue()[0].   cast<AffineMapAttr>().getValue().getNumDims() ==}] # n # [{}]>; +class HasOperandsOfType<string type>: CPred<[{+    std::any_of($0.getOperands().begin(), $0.getOperands().end(),

llvm::any_of

tetuante

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Expose subview promotion as a declarative pattern

 #include "mlir/Dialect/StandardOps/Ops.h" #include "mlir/EDSC/Helpers.h" +#include "llvm/ADT/SetVector.h"++using llvm::SetVector;

Don't do this, don't add using directives in a header. Use it in a fully resolved context, or add this to LLVM.h

tetuante

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Add a Linalg iterator permutation transformation

 LogicalResult linalgOpToAffineLoops(PatternRewriter &rewriter, Operation *op); // Rewrite a linalg.generic into a suitable vector.contraction op. LogicalResult vectorizeGenericOp(PatternRewriter &rewriter, Operation *op); +// Emits a `generic` or `indexed_generic` operation with the `indexing_maps` and

// -> ///

tetuante

comment created time in 2 months

pull request commenttensorflow/mlir

More affine expr simplifications for floordiv and mod

Looks like no-one added the pull tag. Sorry about that.

bondhugula

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Add a Linalg iterator permutation transformation

 LogicalResult linalgOpToLoops(PatternRewriter &rewriter, Operation *op); template <typename ConcreteOp> LogicalResult linalgOpToAffineLoops(PatternRewriter &rewriter, Operation *op); +// Emits a `generic` or `indexed_generic` operation with the `indexing_maps` and+// `iterator_types` permutated according to `permutation`.+LogicalResult permuteGenericLinalgOp(+    PatternRewriter &rewriter, Operation *op, ArrayRef<unsigned> permutation, StringRef linalgMarker);

This looks like it needs clang-format.

tetuante

comment created time in 2 months

Pull request review commenttensorflow/mlir

[Linalg] Add a Linalg iterator permutation transformation

 bool mlir::linalg::detail::isProducedByOpOfTypeImpl(   }   return false; }++LogicalResult+mlir::linalg::permuteGenericLinalgOp(PatternRewriter &rewriter, Operation *op,+                                     ArrayRef<unsigned> permutation,+                                     StringRef linalgMarker) {+  // If permutation is empty, there is nothing to be done.+  if (permutation.size() == 0)+    return failure();++  auto linOp = cast<LinalgOp>(op);+  auto permutationMap =+      inversePermutation(AffineMap::getPermutationMap(permutation, rewriter.getContext()));+  SmallVector<AffineMap, 4> newIndexingMap;+  auto indexingMaps = linOp.getAttrOfType<ArrayAttr>("indexing_maps").getValue();+  for (unsigned i = 0, e = linOp.getNumInputsAndOutputs(); i != e; ++i) {+    AffineMap m = indexingMaps[i].cast<AffineMapAttr>().getValue().compose(permutationMap);+    newIndexingMap.push_back(m);+  }+  auto itTypes = linOp.getAttrOfType<ArrayAttr>("iterator_types").getValue();+  SmallVector<StringRef, 4> itTypesVector;+  for (unsigned i = 0, e = itTypes.size(); i != e; ++i)+    itTypesVector.push_back(itTypes[i].cast<StringAttr>().getValue());+  applyPermutationToVector(itTypesVector, permutation);+  op->setAttr("indexing_maps",+              rewriter.getAffineMapArrayAttr(llvm::makeArrayRef(newIndexingMap)));

Is makeArrayRef actually needed in either of these cases?

tetuante

comment created time in 2 months

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