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Rodrigo A. Melo rodrigomelo9 I-TERA Bs As, Argentina www.linkedin.com/in/rodrigoalejandromelo Digital Electronic Engineer. Interested in projects that involve FPGA devices and/or GNU/Linux.

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A getting started presentation (with examples) about how to use FLOSS for FPGA development.

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Library of utilities such as cores, procedures and functions, commonly shared between FPGA projects.

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A set of Tcl and Python scripts which helps to use FPGA development tools from command line in a vendor independent way

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This project is about FPGA hard blocks and board features. Examples ready to use and verified in hardware.

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Documentation, demos and basic support for this board, developed by INTI - CMNB as part of the CIAA project

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GuideLines for HDL projects

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pull request commentVUnit/vunit

Add Cadence Xcelium support

Ok @cmarqu let me know if you take a look. I will be working into a unified Cadence interface to be inherited by Incisive and Xcelium.

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pull request commentVUnit/vunit

Add Cadence Xcelium support

@LarsAsplund @cmarqu @umarcor here is an update, to define possible next steps. In the current state of this PR:

  • pytest tests/lint/ pass
  • pytest tests/unit/ pass (also the added test_xcelium_interface.py)
  • pytest tests/acceptance presents a lot of fails (log here)
  • examples/vhdl/user_guide pass
  • examples/verilog/user_guide pass after run python3 tools/xcelium_verilog_fixup.py
  • I have another branch to inherit incisive from xcelium as suggested by @umarcor (https://github.com/rodrigomelo9/vunit/pull/1 where I need help because I have doubts about Vunit's internals)
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pull request commentrodrigomelo9/vunit

Modified to inherit Incisive from Xcelium

@umarcor @cmarqu could you review this PR? tests/unit/test_incisive_interface.py is completely broken after these changes. I solved some complaints with:

$ git diff vunit/sim_if/incisive.py
diff --git a/vunit/sim_if/incisive.py b/vunit/sim_if/incisive.py
index b651bffb..8e832cb6 100644
--- a/vunit/sim_if/incisive.py
+++ b/vunit/sim_if/incisive.py
@@ -9,7 +9,7 @@ Interface for the Cadence Incisive simulator
 """
 
 from ..vhdl_standard import VHDL
-from . import ListOfStringOption
+from . import run_command, ListOfStringOption
 from .xcelium import XceliumInterface

And then, renaming irun by xrun in several parts of tests/unit/test_incisive_interface.py, but not sure if the path to go. I am open to suggestions :-D

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pull request commentrodrigomelo9/vunit

Modified to inherit Incisive from Xcelium

Solved :-D (this particular problem, I am dealing with others :P)

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pull request commentVUnit/vunit

Add Cadence Xcelium support

Hi @umarcor

I perform the change to inherit Incisive from Xcelium, but I have pytest issues where I need help. I open https://github.com/rodrigomelo9/vunit/pull/1 to work on that.

rodrigomelo9

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PR opened rodrigomelo9/vunit

Modified to inherit Incisive from Xcelium

@umarcor I need help here

I tried to inherit Incisive from Xcelium. It was relatively simple, but I am not sure about how to solve a lot of pytests issues.

Before changes, the following was ok:

pytest tests/lint/
pytest tests/unit/

After changes, there are a lot of issues, where maybe you can help (after all, you suggested this change :smiley:)

With pytest tests/lint/ there are a lot of

tests/lint/test_pylint.py:16: in <module>
    from tests.lint.test_pycodestyle import get_files_and_folders
<frozen importlib._bootstrap>:991: in _find_and_load
    ???
<frozen importlib._bootstrap>:975: in _find_and_load_unlocked
    ???
<frozen importlib._bootstrap>:671: in _load_unlocked
    ???
/usr/local/lib/python3.8/dist-packages/_pytest/assertion/rewrite.py:170: in exec_module
    exec(co, module.__dict__)
tests/lint/test_pycodestyle.py:16: in <module>
    from vunit import ROOT as RSTR
vunit/__init__.py:13: in <module>
    from vunit.ui import VUnit
vunit/ui/__init__.py:24: in <module>
    from ..vunit_cli import VUnitCLI
vunit/vunit_cli.py:40: in <module>
    from vunit.sim_if.factory import SIMULATOR_FACTORY
vunit/sim_if/factory.py:175: in <module>
    SIMULATOR_FACTORY = SimulatorFactory()
vunit/sim_if/factory.py:157: in __init__
    self._compile_options = self._extract_compile_options()
vunit/sim_if/factory.py:49: in _extract_compile_options
    assert opt.name.startswith(sim_class.name + ".")
E   AssertionError

With pytest tests/unit/ there a lot of

tests/unit/test_xcelium_interface.py:20: in <module>
    from vunit.project import Project
vunit/__init__.py:13: in <module>
    from vunit.ui import VUnit
vunit/ui/__init__.py:24: in <module>
    from ..vunit_cli import VUnitCLI
vunit/vunit_cli.py:40: in <module>
    from vunit.sim_if.factory import SIMULATOR_FACTORY
vunit/sim_if/factory.py:175: in <module>
    SIMULATOR_FACTORY = SimulatorFactory()
vunit/sim_if/factory.py:157: in __init__
    self._compile_options = self._extract_compile_options()
vunit/sim_if/factory.py:49: in _extract_compile_options
    assert opt.name.startswith(sim_class.name + ".")
E   AssertionError

As you can see, in both cases related to assert opt.name.startswith(sim_class.name + ".")

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