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enjoy-digital/litex 824

Build your hardware, easily!

google/verible 319

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

olofk/serv 279

SERV - The SErial RISC-V CPU

enjoy-digital/litedram 170

Small footprint and configurable DRAM core

enjoy-digital/usb3_pipe 76

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

im-tomu/valentyusb 69

FPGA USB stack written in LiteX

antmicro/fastvdma 35

Antmicro's fast, vendor-neutral DMA IP in Chisel

antmicro/usb-test-suite-build 28

Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores

chipsalliance/verilator 15

Verilator open-source SystemVerilog simulator and lint system

push eventantmicro/kokoro-test

Piotr Zierhoffer

commit sha 8ad435e62cec498bc40b606105df5e8b8e234353

Increase Kokoro timeouts

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PR opened olofk/serv

break out verilator fileset for use with v < 4.030

Ensure vlog_tb_utils is not included in the file-set for verilator runs. Verilator versions < 4.030 do not implement dumpfile and dumpvar, which are used in vlog_tb_utils.

+9 -4

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pr created time in 4 hours

Pull request review commentgoogle/verible

Add suggest_parentheses rule for Verible::Linter

+// Copyright 2017-2020 The Verible Authors.+//+// Licensed under the Apache License, Version 2.0 (the "License");+// you may not use this file except in compliance with the License.+// You may obtain a copy of the License at+//+//      http://www.apache.org/licenses/LICENSE-2.0+//+// Unless required by applicable law or agreed to in writing, software+// distributed under the License is distributed on an "AS IS" BASIS,+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.+// See the License for the specific language governing permissions and+// limitations under the License.++#include "verilog/analysis/checkers/suggest_parentheses_rule.h"+++#include "common/analysis/syntax_tree_linter_test_utils.h"+#include "verilog/analysis/verilog_analyzer.h"++namespace verilog {+namespace analysis {+namespace {++using verible::LintTestCase;+using verible::RunLintTestCases;++TEST(SuggestParenthesesTest, AcceptTests) {

Since this contains a mix of positive and negative tests, rename AcceptTests to something like Various.

omarahmed1111

comment created time in 6 hours

Pull request review commentgoogle/verible

Add suggest_parentheses rule for Verible::Linter

 bool ConstantIntegerValue(const verible::Symbol& expr, int* value) {   return absl::SimpleAtoi(text, value); } ++const verible::Symbol* UnwrapExpression(const verible::Symbol& expr) {+  +  const auto& node = verible::SymbolCastToNode(expr);+  const auto tag = static_cast<verilog::NodeEnum>(node.Tag().tag);++  if (expr.Kind() == SymbolKind::kLeaf || tag != NodeEnum::kExpression) {+    return &expr;+  }++  const auto& children = node.children();+  return children.front().get();+}++const verible::Symbol* GetConditionExpressionPredicate(const verible::Symbol& condition_expr) {+  return GetSubtreeAsSymbol(condition_expr, NodeEnum::kConditionExpression, 0);+}++const verible::Symbol* GetConditionExpressionTrueCase(const verible::Symbol& condition_expr) {+  return GetSubtreeAsSymbol(condition_expr, NodeEnum::kConditionExpression, 2);+}++const verible::Symbol* GetConditionExpressionFalseCase(const verible::Symbol& condition_expr) {+  return GetSubtreeAsSymbol(condition_expr, NodeEnum::kConditionExpression, 4);+}

Let's add unit tests for these, so that should any of these get restructured, we'll know to fix them in one place.

Example unit tests. Or look at many other CST/*_test.cc files.

A typical recipe for unit testing these extractor functions:

  1. FindAll of the outer structure of interest (might need to write a quick function for this too), in this case, condition expressions.
  2. Write test cases, tagging the substring of text that corresponds to what an accessor function should return: condition, true case, false case.
  3. Pass the array of test cases to TestVerilogSyntaxRangeMatches (this is where you call FindAll and possibly other functions to refine your search).
omarahmed1111

comment created time in 5 hours

Pull request review commentgoogle/verible

Add suggest_parentheses rule for Verible::Linter

 bool ConstantIntegerValue(const verible::Symbol& expr, int* value) {   return absl::SimpleAtoi(text, value); } ++const verible::Symbol* UnwrapExpression(const verible::Symbol& expr) {+  +  const auto& node = verible::SymbolCastToNode(expr);

This will terminate with an assert failure if passed a leaf, so suggest checking expr.Kind() first before doing this cast.

omarahmed1111

comment created time in 6 hours

Pull request review commentgoogle/verible

Add suggest_parentheses rule for Verible::Linter

+// Copyright 2017-2020 The Verible Authors.+//+// Licensed under the Apache License, Version 2.0 (the "License");+// you may not use this file except in compliance with the License.+// You may obtain a copy of the License at+//+//      http://www.apache.org/licenses/LICENSE-2.0+//+// Unless required by applicable law or agreed to in writing, software+// distributed under the License is distributed on an "AS IS" BASIS,+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.+// See the License for the specific language governing permissions and+// limitations under the License.++#include "verilog/analysis/checkers/suggest_parentheses_rule.h"+++#include "common/analysis/syntax_tree_linter_test_utils.h"+#include "verilog/analysis/verilog_analyzer.h"++namespace verilog {+namespace analysis {+namespace {++using verible::LintTestCase;+using verible::RunLintTestCases;++TEST(SuggestParenthesesTest, AcceptTests) {+  constexpr int kTag = 293;  // don't care++  const std::initializer_list<LintTestCase> kSuggestParenthesesTestCases = {+      // Non rule violation cases.+      {""},+      {"module m;\nendmodule\n"},+      {"module m;\ninitial begin end\nendmodule"},+      {"module m;\n", "assign foo = condition_a? a : b;", "\nendmodule"},+      {"module m;\n", "assign foo = condition_a? (condition_b? a : b) : c;", "\nendmodule"},+      {"module m;\n", "assign foo = condition_a? (condition_b? a : b) : (condition_c? c : d);", "\nendmodule"},+      {"module m;\n", "assign foo = condition_a? (condition_b? (condition_c? a : b) : c) : d;", "\nendmodule"},+      {"module m;\n", "assign foo = condition_a? (condition_b? a : b) : condition_c? c : d;", "\nendmodule"},+      {"module m;\n", "parameter foo = condition_a? a : b;" ,"\nendmodule"},+      {"module m;\n", "always @(posedge clk) begin\n left <= condition_a? a : b; \nend", "\nendmodule"},+      {"function f;\n g = h(condition_a? a : b); \nendfunction"},+      {"module m;\n", "always @(posedge clk)\n", "case (condition_a? a : b)\n", "default :;\n", "endcase\n", "\nendmodule"},+      // Rule Violation cases.+      {"module m;\n assign foo = condition_a? ", {kTag, "condition_b"}, "? a : b : c;\nendmodule"},

When we do create a violation, let's mark the whole true-case subexpression, instead of just the first token. (So on this line, {kTag, "condition_b ? a : b"}.)

Use the StringSpanOfSymbol function. Examples.

This way, it makes it clear to the reader (or fixer tool) where to add the parentheses.

omarahmed1111

comment created time in 6 hours

pull request commentSymbiFlow/symbiflow-examples

xc7: Use Conda packages from LiteX-Hub channel

@ajelinski if there is the 5e6370a package on litex-hub we could use it as it would be in line with the archdefs packages. Otherwise yes, we should wait for those PRs to be merged

ajelinski

comment created time in 6 hours

pull request commentSymbiFlow/symbiflow-examples

xc7: Use Conda packages from LiteX-Hub channel

Versions are in sync with https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1795. I guess after that PR and https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1747 are merged Symbiflow's install packages can be updated and the problem should be gone @acomodi?

ajelinski

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pull request commentSymbiFlow/symbiflow-examples

xc7: Use Conda packages from LiteX-Hub channel

Yep, yosys-plugins are the newest one in this PR with the design_introspection update, and the Symbiflow install packages do not have the fix for that in the synth.tcl yosys script.

The correct and working plugins version should be 5e6370a

ajelinski

comment created time in 7 hours

pull request commentSymbiFlow/symbiflow-examples

xc7: Use Conda packages from LiteX-Hub channel

Failed on xc7-linux

cd build && symbiflow_synth -t top -v /home/runner/work/symbiflow-examples/symbiflow-examples/xc7/linux_litex_demo/baselitex_arty.v /home/runner/work/symbiflow-examples/symbiflow-examples/xc7/linux_litex_demo/VexRiscv_Linux.v -d artix7 -p xc7a35tcsg324-1 -x /home/runner/work/symbiflow-examples/symbiflow-examples/xc7/linux_litex_demo/arty.xdc 2>&1 > /dev/null
ERROR: Couldn't find port [get_ports]
make: *** [Makefile:33: build/top.eblif] Error 1
ajelinski

comment created time in 7 hours

PR opened SymbiFlow/sv-tests

New test from recent IVL_UVM testsuite
+38 -0

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issue openedSymbiFlow/sv-tests

dependabot hasn't updated slang in a few weeks

I don't know much about how dependabot works -- any idea what might be wrong here? I don't see any opened or closed pull requests from it for slang for several weeks.

created time in 9 hours

issue openedSymbiFlow/sv-tests

Adding new tests - guide?

Hi, If I want to add few tests to this great repo, the procedure is described on the structure of the test. On the check-in/pull-request, is it the common flow as in:

https://jarv.is/notes/how-to-pull-request-fork-github/ (For instance)

Thanks Srini

created time in 10 hours

pull request commentenjoy-digital/litex

rocket: Fix UB due to optimised away DFFs

@daveshah1 Thanks for tracking this down -- it does indeed fix the issue!

daveshah1

comment created time in 10 hours

push eventenjoy-digital/litex

David Shah

commit sha 61895bef37bb8854d0f5ed975961777327fb0806

rocket: Fix UB due to optimised away DFFs As both clock and async reset for the debug DFFs were 0, and there was no initial value on them, they were being validly optimised away by newer Yosys versions to 1'bx which was propagating into and breaking the core. This fixes the problem by tying the async resets to the CPU reset signal. Signed-off-by: David Shah <dave@ds0.me>

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gsomlo

commit sha d9f9b4aeb6c22387f96e9803dd607c734e107bd6

Merge pull request #713 from daveshah1/dave/rocket-reset-fix rocket: Fix UB due to optimised away DFFs

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PR merged enjoy-digital/litex

rocket: Fix UB due to optimised away DFFs

As both clock and async reset for the debug DFFs were 0, and there was no initial value on them, they were being validly optimised away by newer Yosys versions to 1'bx which was propagating into and breaking the core.

This fixes the problem by tying the async resets to the CPU reset signal.

Thus far only tested with my hacky post-early-synth simulation test, I'll have hardware results in half an hour or so -- edit, seems good on hardware too.

+2 -2

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daveshah1

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push eventantmicro/verible-ibex-indexer

github-actions[bot]

commit sha a2a9682b10e3bc74ebd08f41ca859e0c76dbde22

Update revisions ** ibex: ** 4735a26 Avoid use of the term "sanity test" in icache UVM testbench 4852e30 Update lowrisc_ip to lowRISC/opentitan@e619fc60 31a18ad Clear MAKEFLAGS when running dvsim.py 3d80415 Delete dv/uvm/data and point DV code at the vendored version 623402c Vendor in hw/dv/{data,tools} from OpenTitan 690f8af Update paths for vendored DV code

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SymbiFlow Robot

commit sha 401d9e19f8e033c5d9f423914b8ae927acbb30ff

Deploy v0.0-1735-g8bb3c991b675 (build 0bcfd524-1633-4c71-9981-b16f900eac4d) Build from https://github.com/SymbiFlow/sv-tests/commit/8bb3c991b6753e9bc74e6727cf3ea355b9b2e368

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issue openedSymbiFlow/sv-tests

Fresh clone sv-tests takes 4-5 hours - is this common?

Hello, I am trying a fresh git clone of sv-tests on a Linux laptop (not very high-end, but does run EDA tools and is connected to highspeed Ethernet (Tried WiFi first, then moved to Ethernet). The process seems to take multiple hours > 4 hours. Is this common? I am sure it is first-time-only issue, later should be faster, but just wanted to check with others. Attaching a screenshot.

Any comments appreciated.

Thanks Srini

IMG_20201128_172147

created time in 11 hours

PR opened enjoy-digital/litex

rocket: Fix UB due to optimised away DFFs

As both clock and async reset for the debug DFFs were 0, and there was no initial value on them, they were being validly optimised away by newer Yosys versions to 1'bx which was propagating into and breaking the core.

This fixes the problem by tying the async resets to the CPU reset signal.

Thus far only tested with my hacky post-early-synth simulation test, I'll have hardware results in half an hour or so.

+2 -2

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Florent Kermarrec

commit sha 869e50ade89fb10acc2d2f1c1cddb59e2f1e0e18

soc/cores/prbs: minor cosmetic cleanups.

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Florent Kermarrec

commit sha c491c60b7d9ee890f33ce33db199b733b0527dd7

soc/cores/prbs/PRBSRX: add pause signal to pause errors counting. Simplify CDC when passing the errors to software by allowing the values to stabilized.

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SymbiFlow Robot

commit sha 4a527eb8f5fc5124c2afcefefde79935dd6a2692

Deploy v0.0-1725-g06a1f21c5a35 (build 38137ac8-3134-450c-b4bf-3b358bced18c) Build from https://github.com/SymbiFlow/sv-tests/commit/06a1f21c5a352b3fb1a7f3c4c43880052f1fb6c6

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issue openedenjoy-digital/litex

lxsim error: call to member function 'dump' is ambiguous

I'm on macOS 10.14, and using Python 3.8.2 in an Anaconda virtual environment named FPGA. I installed litex by:

$ cd ~/Developer
$ git clone https://github.com/enjoy-digital/litex.git
$ cd litex
$ conda activate FPGA
$ ./litex_setup.py init install --user

Afterwards, I did lxsim --cpu-type=vexriscv, and an error occured when I did lxsim --cpu-type=vexriscv. Please check the error log below:

$ lxsim --cpu-type=vexriscv
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-11-28 17:51:51)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (3)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- main_ram
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (6)
- ctrl           : 0
- cpu            : 1
- identifier_mem : 2
- uart_phy       : 3
- uart           : 4
- timer0         : 5
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
make: Nothing to be done for `all'.
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       i2c.o
 CC       memtest.o
 CC       sim_debug.o
 AR       libbase.a
 AR       libbase-nofloat.a
 CC       sdram.o
 CC       bist.o
 AR       liblitedram.a
 CC       udp.o
 CC       mdio.o
 AR       libliteeth.a
 CC       spiflash.o
 AR       liblitespi.a
make: Nothing to be done for `all'.
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
 CC       sata.o
 AR       liblitesata.a
 CC       isr.o
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       main.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /Users/nalzok/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 20.79KiB 	(64.95%)
RAM usage: 1.63KiB 	(20.41%)

make: Nothing to be done for `all'.
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       i2c.o
 CC       memtest.o
 CC       sim_debug.o
 AR       libbase.a
 AR       libbase-nofloat.a
 CC       sdram.o
 CC       bist.o
 AR       liblitedram.a
 CC       udp.o
 CC       mdio.o
 AR       libliteeth.a
 CC       spiflash.o
 AR       liblitespi.a
make: Nothing to be done for `all'.
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
 CC       sata.o
 AR       liblitesata.a
 CC       isr.o
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       main.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /Users/nalzok/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 20.79KiB 	(64.95%)
RAM usage: 1.63KiB 	(20.41%)

Traceback (most recent call last):
  File "/Users/nalzok/.local/bin/lxsim", line 33, in <module>
    sys.exit(load_entry_point('litex', 'console_scripts', 'lxsim')())
  File "/Users/nalzok/Developer/litex/litex/tools/litex_sim.py", line 421, in main
    vns = builder.build(
  File "/Users/nalzok/Developer/litex/litex/soc/integration/builder.py", line 217, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/Users/nalzok/Developer/litex/litex/soc/integration/soc.py", line 1054, in build
    return self.platform.build(self, *args, **kwargs)
  File "/Users/nalzok/Developer/litex/litex/build/sim/platform.py", line 54, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/Users/nalzok/Developer/litex/litex/build/sim/verilator.py", line 235, in build
    _compile_sim(build_name, verbose)
  File "/Users/nalzok/Developer/litex/litex/build/sim/verilator.py", line 154, in _compile_sim
    raise OSError("Subprocess failed with {}\n{}".format(p.returncode, "\n".join(error_messages)))
OSError: Subprocess failed with 2
mkdir -p modules
/Applications/Xcode.app/Contents/Developer/usr/bin/make -C modules -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/Makefile
mkdir -p xgmii_ethernet
/Applications/Xcode.app/Contents/Developer/usr/bin/make MOD=xgmii_ethernet -C xgmii_ethernet -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile
make[2]: Nothing to be done for `all'.
cp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so
mkdir -p ethernet
/Applications/Xcode.app/Contents/Developer/usr/bin/make MOD=ethernet -C ethernet -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/ethernet/Makefile
make[2]: Nothing to be done for `all'.
cp ethernet/ethernet.so ethernet.so
mkdir -p serial2console
/Applications/Xcode.app/Contents/Developer/usr/bin/make MOD=serial2console -C serial2console -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/serial2console/Makefile
make[2]: Nothing to be done for `all'.
cp serial2console/serial2console.so serial2console.so
mkdir -p serial2tcp
/Applications/Xcode.app/Contents/Developer/usr/bin/make MOD=serial2tcp -C serial2tcp -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/serial2tcp/Makefile
make[2]: Nothing to be done for `all'.
cp serial2tcp/serial2tcp.so serial2tcp.so
mkdir -p clocker
/Applications/Xcode.app/Contents/Developer/usr/bin/make MOD=clocker -C clocker -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/clocker/Makefile
make[2]: Nothing to be done for `all'.
cp clocker/clocker.so clocker.so
mkdir -p spdeeprom
/Applications/Xcode.app/Contents/Developer/usr/bin/make MOD=spdeeprom -C spdeeprom -f /Users/nalzok/Developer/litex/litex/build/sim/core/modules/spdeeprom/Makefile
make[2]: Nothing to be done for `all'.
cp spdeeprom/spdeeprom.so spdeeprom.so
mkdir -p /Users/nalzok/build/sim/gateware/obj_dir
cc -c -I/usr/local/include/ -o /Users/nalzok/build/sim/gateware/obj_dir/libdylib.o /Users/nalzok/Developer/litex/litex/build/sim/core/libdylib.c
cc -c -I/usr/local/include/ -o /Users/nalzok/build/sim/gateware/obj_dir/modules.o /Users/nalzok/Developer/litex/litex/build/sim/core/modules.c
cc -c -I/usr/local/include/ -o /Users/nalzok/build/sim/gateware/obj_dir/pads.o /Users/nalzok/Developer/litex/litex/build/sim/core/pads.c
cc -c -I/usr/local/include/ -o /Users/nalzok/build/sim/gateware/obj_dir/parse.o /Users/nalzok/Developer/litex/litex/build/sim/core/parse.c
cc -c -I/usr/local/include/ -o /Users/nalzok/build/sim/gateware/obj_dir/sim.o /Users/nalzok/Developer/litex/litex/build/sim/core/sim.c
verilator -Wno-fatal -O3 --cc /Users/nalzok/Developer/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /Users/nalzok/build/sim/gateware/sim.v  --top-module sim --exe \
		-DPRINTF_COND=0 \
		sim_init.cpp /Users/nalzok/Developer/litex/litex/build/sim/core/veril.cpp libdylib.o modules.o pads.o parse.o sim.o \
		--top-module sim \
		 \
		-CFLAGS "-I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core" \
		-LDFLAGS "-L/usr/local/lib -lpthread -ljson-c -lm -lstdc++ -ldl -levent" \
		--trace \
		 \
		 \
		--unroll-count 256 \
		--output-split 5000 \
		--output-split-cfuncs 500 \
		--output-split-ctrace 500 \
		 \
		-Wno-BLKANDNBLK \
		-Wno-WIDTH
%Warning-CASEINCOMPLETE: /Users/nalzok/build/sim/gateware/sim.v:1075:3: Case values incompletely covered (example pattern 0x3)
                                                                      : ... In instance sim
 1075 |   case (csr_bankarray_interface0_bank_bus_adr[1:0])
      |   ^~~~
                         ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
make -j -C /Users/nalzok/build/sim/gateware/obj_dir -f Vsim.mk Vsim
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o veril.o /Users/nalzok/Developer/litex/litex/build/sim/core/veril.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o sim_init.o ../sim_init.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o verilated.o /opt/local/share/verilator/include/verilated.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o verilated_dpi.o /opt/local/share/verilator/include/verilated_dpi.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o verilated_vcd_c.o /opt/local/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim.o Vsim.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_sim.o Vsim_sim.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_VexRiscv.o Vsim_VexRiscv.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_VexRiscv__1.o Vsim_VexRiscv__1.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_VexRiscv__2.o Vsim_VexRiscv__2.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim__Slow.o Vsim__Slow.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_sim__Slow.o Vsim_sim__Slow.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__Slow.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim_VexRiscv__1__Slow.o Vsim_VexRiscv__1__Slow.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim__Dpi.o Vsim__Dpi.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim__Trace.o Vsim__Trace.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim__Syms.o Vsim__Syms.cpp
/usr/bin/clang++  -I.  -MMD -I/opt/local/share/verilator/include -I/opt/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -I/usr/local/include/ -I/Users/nalzok/Developer/litex/litex/build/sim/core   -c -o Vsim__Trace__Slow.o Vsim__Trace__Slow.cpp
/Users/nalzok/Developer/litex/litex/build/sim/core/veril.cpp:75:10: error: call to member function 'dump' is ambiguous
    tfp->dump(main_time);
    ~~~~~^~~~
/opt/local/share/verilator/include/verilated_vcd_c.h:391:10: note: candidate function
    void dump(vluint64_t timeui) { m_sptrace.dump(timeui); }
         ^
/opt/local/share/verilator/include/verilated_vcd_c.h:394:10: note: candidate function
    void dump(double timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
         ^
/opt/local/share/verilator/include/verilated_vcd_c.h:395:10: note: candidate function
    void dump(vluint32_t timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
         ^
/opt/local/share/verilator/include/verilated_vcd_c.h:396:10: note: candidate function
    void dump(int timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
         ^
1 error generated.
make[1]: *** [veril.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [sim] Error 2

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commit sha dc755bff2a7ff5a1271225f58704dc8c58cd62b6

build(deps): bump third_party/tools/Surelog from `76f7838` to `dd1b478` Bumps [third_party/tools/Surelog](https://github.com/alainmarcel/Surelog) from `76f7838` to `dd1b478`. - [Release notes](https://github.com/alainmarcel/Surelog/releases) - [Commits](https://github.com/alainmarcel/Surelog/compare/76f7838428ce0a81c7471ed2d76ef0752b338a9e...dd1b478bb2237ec5c42d5d29578ceae867a12b97) Signed-off-by: dependabot-preview[bot] <support@dependabot.com>

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commit sha 8bb3c991b6753e9bc74e6727cf3ea355b9b2e368

Merge pull request #1178 from SymbiFlow/dependabot/submodules/third_party/tools/Surelog-dd1b478

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build(deps): bump third_party/tools/Surelog from `76f7838` to `dd1b478` dependencies

Bumps third_party/tools/Surelog from 76f7838 to dd1b478. <details> <summary>Commits</summary> <ul> <li><a href="https://github.com/alainmarcel/Surelog/commit/dd1b478bb2237ec5c42d5d29578ceae867a12b97"><code>dd1b478</code></a> Merge pull request <a href="https://github-redirect.dependabot.com/alainmarcel/Surelog/issues/928">#928</a> from alainmarcel/alainmarcel-patch-1</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/241bf562ca31e87482b2cd9f3c31f5342ef37867"><code>241bf56</code></a> Several fixes for arithmetic errors vs elaboration</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/4dc19edbf640e7fe7ce7cf8545b1a1f77b54ab3b"><code>4dc19ed</code></a> Update README.md</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/dbe7b27f901c2febb75613fa2fcd188d6c868137"><code>dbe7b27</code></a> Update README.md</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/5679a484f432c9c865ca00646f5164b782a1b667"><code>5679a48</code></a> Update README.md</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/10ff0c255bf7e6c8087ce4b4c7636f15e1f1a215"><code>10ff0c2</code></a> Update README.md</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/534f9f35bb25c7b4baac994b6928ff19f09ba50c"><code>534f9f3</code></a> Merge pull request <a href="https://github-redirect.dependabot.com/alainmarcel/Surelog/issues/924">#924</a> from alainmarcel/alainmarcel-patch-1</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/cad56a6a7e34dc79b6a67575b0f0aedbbb0a5b00"><code>cad56a6</code></a> Fix Ariane bug (ulong long expr)</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/934487b3879802651dc6c40eb8bf415bbbdd6e00"><code>934487b</code></a> Merge pull request <a href="https://github-redirect.dependabot.com/alainmarcel/Surelog/issues/923">#923</a> from alainmarcel/alainmarcel-patch-1</li> <li><a href="https://github.com/alainmarcel/Surelog/commit/8011553caf344401ea3eab9b74eb366fa69262ca"><code>8011553</code></a> Operator associativity</li> <li>Additional commits viewable in <a href="https://github.com/alainmarcel/Surelog/compare/76f7838428ce0a81c7471ed2d76ef0752b338a9e...dd1b478bb2237ec5c42d5d29578ceae867a12b97">compare view</a></li> </ul> </details> <br />

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build(deps): bump third_party/tools/icarus from `359b2b6` to `99bb0d1` Bumps [third_party/tools/icarus](https://github.com/steveicarus/iverilog) from `359b2b6` to `99bb0d1`. - [Release notes](https://github.com/steveicarus/iverilog/releases) - [Commits](https://github.com/steveicarus/iverilog/compare/359b2b65c2f015191ec05109d82e91ec22569a9b...99bb0d15b22786b5421a7ab3fa239e717887ed32) Signed-off-by: dependabot-preview[bot] <support@dependabot.com>

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Merge pull request #1177 from SymbiFlow/dependabot/submodules/third_party/tools/icarus-99bb0d1

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build(deps): bump third_party/tools/icarus from `359b2b6` to `99bb0d1` dependencies

Bumps third_party/tools/icarus from 359b2b6 to 99bb0d1. <details> <summary>Commits</summary> <ul> <li><a href="https://github.com/steveicarus/iverilog/commit/99bb0d15b22786b5421a7ab3fa239e717887ed32"><code>99bb0d1</code></a> Report error if command file is not properly terminated.</li> <li><a href="https://github.com/steveicarus/iverilog/commit/2dcbfca5d973bcd94fc03232d7d25895a1177ced"><code>2dcbfca</code></a> Clarify "Standard inconsistency" warning</li> <li><a href="https://github.com/steveicarus/iverilog/commit/dee68faf8056f290788cd507972beb1396efd584"><code>dee68fa</code></a> Merge pull request <a href="https://github-redirect.dependabot.com/steveicarus/iverilog/issues/396">#396</a> from steveicarus/array-copy</li> <li><a href="https://github.com/steveicarus/iverilog/commit/3c2fb6a601c2baf82ab1bbbadce0b28dd2a82446"><code>3c2fb6a</code></a> Fix dynamic array assignment to make a copy of the rvalue.</li> <li><a href="https://github.com/steveicarus/iverilog/commit/159af4d4ba28739b0b74bf158a928550b7342abb"><code>159af4d</code></a> In Windows, export VPI functions from vvp.exe (GitHub issue <a href="https://github-redirect.dependabot.com/steveicarus/iverilog/issues/395">#395</a>)</li> <li><a href="https://github.com/steveicarus/iverilog/commit/b0b44fdd8a1bd007ac62a5a20408fe6bda1d21e1"><code>b0b44fd</code></a> Support passing class objects as task/function arguments (GitHub issure <a href="https://github-redirect.dependabot.com/steveicarus/iverilog/issues/391">#391</a>)</li> <li><a href="https://github.com/steveicarus/iverilog/commit/55e06db6932960407dea0493cf91fcc2580a9290"><code>55e06db</code></a> Support calls to inherited methods without "this." prefix (GitHub issue <a href="https://github-redirect.dependabot.com/steveicarus/iverilog/issues/388">#388</a>).</li> <li><a href="https://github.com/steveicarus/iverilog/commit/7277f4e8079c7a2f0241020206cf8795ece05bf7"><code>7277f4e</code></a> Merge pull request <a href="https://github-redirect.dependabot.com/steveicarus/iverilog/issues/394">#394</a> from steveicarus/super-new-handling</li> <li><a href="https://github.com/steveicarus/iverilog/commit/919fd22a792dbfbd996e97d5c7e4dcfc5f052069"><code>919fd22</code></a> Handle the special case that constructor only chains.</li> <li><a href="https://github.com/steveicarus/iverilog/commit/156644d91e1fa13fccc9fe9df6555a23803ee2f5"><code>156644d</code></a> Detect and complain about some constructor chain errors</li> <li>Additional commits viewable in <a href="https://github.com/steveicarus/iverilog/compare/359b2b65c2f015191ec05109d82e91ec22569a9b...99bb0d15b22786b5421a7ab3fa239e717887ed32">compare view</a></li> </ul> </details> <br />

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pull request commentSymbiFlow/sv-tests

build(deps): bump third_party/tools/odin_ii from `5bded3e` to `5ff8613`

One of your CI runs failed on this pull request, so Dependabot won't merge it.

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dependabot-preview[bot]

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