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joshuisken/blinky 0

Example LED blinking project for your FPGA dev board of choice

joshuisken/edalize 0

An abstraction library for interfacing EDA tools

joshuisken/myhdl 0

The MyHDL development repository

joshuisken/opentitan 0

OpenTitan: Open source silicon root of trust

joshuisken/rhea 0

A collection of MyHDL cores and tools for complex digital circuit design

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Zimbra Docker and related scripts

issue commentmyhdl/myhdl

traceSignals incorrectly writes real value signal to VCD

Here is a simple model of ideal Digital to Analog Converter (DAC):

`from myhdl import modbv, Signal, delay, always, Simulation, traceSignals, instance, now

import numpy as np

def clock_source(clock, frequency): period = 1 / frequency / 10 ** (-9) # ns half_period = delay(round(period / 2))

@always(half_period)
def clksrc():
    clock.next = not clock

return clksrc

def digital_sin_source(clock, sine, frequency, bits): out_range = 2 ** (bits - 1)

@always(clock.posedge)
def sinsrc():
    sine.next = int(out_range * np.sin(2 * np.pi * frequency * now() / 10 ** 9))

return sinsrc

def ideal_dac(clock, digital, analog, bits, amin=-1, amax=1): step = (amax - amin) / 2 ** bits

@always(clock.posedge)
def dac():
    analog.next = amin + step * digital

return dac

def test_ideal_dac(): bits = 8 clock = Signal(bool(0)) digital = Signal(modbv(0, min=-(2 ** (bits - 1)), max=2 ** (bits - 1))) analog = Signal(float(0))

clksrc = clock_source(clock, 100 * 10 ** 6)
sine = digital_sin_source(clock, digital, 10 * 10 ** 3, bits=bits)
dac = ideal_dac(clock, digital, analog, bits=bits)

@instance
def test():
    yield delay(10)

return clksrc, sine, dac, test

traceSignals.filename = 'test' test_inst = traceSignals(test_ideal_dac) Simulation(test_inst).run(100000) `

This code generates test.vcd file. Then I open it in GTKwave (version 3.3.100) and add all signals. The "analog" signal is a real value signal, so I choose in GTKwave: Data Format -> Analog -> Interpolated. But nothing happens. When I locally modified _printVcdStr function and install MyHDL using pip from local files all is ok.

zlobriy

comment created time in 2 days

issue commentmyhdl/myhdl

traceSignals incorrectly writes real value signal to VCD

Can you provide a simple excerpt of code showing the problem ?

zlobriy

comment created time in 2 days

issue openedmyhdl/myhdl

traceSignals incorrectly writes real value signal to VCD

traceSignals function incorrectly writes real value signal to VCD. Verilog Standard states that a real value signal in VCD dump should start with "r" or "R" identifier. But instead, MyHDL creates signal starting with "s". So GTKwave can't make an analog wave. A function _printVcdStr caused this behavior. Just change 's' to 'r'.

created time in 2 days

issue commentmyhdl/myhdl

Verilog parameter support

Yes, that the way it works.

kjleeic

comment created time in 18 days

issue commentmyhdl/myhdl

Verilog parameter support

@cfelton this will replace the parameter with its values, in the generated verilog, isn't it?

kjleeic

comment created time in 18 days

PR closed myhdl/myhdl

Update _toVerilog.py

no the attribute signed in line 1604 originally.

+5 -2

2 comments

1 changed file

TongJoe

pr closed time in 2 months

pull request commentmyhdl/myhdl

Init reset fix

Just updated the PR...

ThomasHornschuh

comment created time in 3 months

PR closed alexforencich/verilog-axis

FIFO reset

I ran into an issue where the FIFO was reset and data became available the cycle after. The FIFO axis-slave hast tready asserted, but the internal write address is not correct in that case. One solution might be to deassert tready for the cycle after the reset. Alternatively the address calculation can provide the correct address immediately after reset. This implements the latter. Also I think the tready signal should be deasserted during reset. The core is definitely not going to be ready to receive data and hence should signal accordingly. I prepared test cases for these fixes and added them to the test bench.

+204 -25

6 comments

3 changed files

LeChuck42

pr closed time in 3 months

pull request commentalexforencich/verilog-axis

FIFO reset

The registers in question have now been removed, so I'm considering this resolved.

LeChuck42

comment created time in 3 months

push eventalexforencich/verilog-axis

Alex Forencich

commit sha 71b6b9f6f2d6d03c1cc9ea41e1452dd9ac3f499d

Prevent shift register inference

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Alex Forencich

commit sha da152a854651c2cf472e442aa2dddccdae356532

Update timing parameters for async FIFO to reflect new pipeline register naming

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push time in 3 months

Pull request review commentmyhdl/myhdl

Init reset fix

 def test_memory_convert():         toVHDL.initial_values = pre_viv  +@block+def init_reset_tb():++    clk = Signal(bool(0))+    reset = ResetSignal(0, active=1, isasync=False)++    s_large = Signal(intbv(0xc0000000)[32:])

@josby, @ThomasHornschuh thanks for the clarification, understand.

ThomasHornschuh

comment created time in 3 months

Pull request review commentmyhdl/myhdl

Init reset fix

 def __call__(self, func, *args, **kwargs):          if isinstance(func, _Block):             if hdl == "VHDL":-                inst = func.convert(hdl='VHDL')+                inst = func.convert(hdl='VHDL',*args, **kwargs)

yes, I agree looks good. If you push that small change I will merge it.

ThomasHornschuh

comment created time in 3 months

push eventalexforencich/verilog-axis

Alex Forencich

commit sha 84cffeca5fbc107e0ec6f69a3f0328b47f669cac

Remove unneeded address registers

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Alex Forencich

commit sha b7ed61b242a602baf2a36a7f20ac0342a8837e72

Rewrite resets

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Alex Forencich

commit sha c9950d56ae21d8e506ff709b23e16858c3e54960

Rewrite full/empty logic

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Alex Forencich

commit sha eb6861cbc48a52e07fd6ded11a3f8217b78dadec

Convert to single always block

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Alex Forencich

commit sha 2f883681d6bc3afe710fbb33622f5e86d94b97cf

Add pararametrizable output pipeline to FIFOs

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Alex Forencich

commit sha ede73b434a313d00c522fcddb3c04333a5f96b06

Add PIPELINE_OUTPUT parameter to FIFO adapter modules

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push time in 3 months

pull request commentalexforencich/verilog-axis

FIFO reset

Well, after doing some investigating, it's unclear why I added that reg in the first place. At the time I was working with the VCU108 board with a XCVU095 FPGA. However, the block RAM on that FPGA doesn't absorb those address registers, and removing them results in the same level of timing performance. For UltraRAMs, I think all inputs need to be registered, both address and data. I'm thinking I will remove that register completely and consider adding parametrizable input registers to aid in timing when using URAMs.

LeChuck42

comment created time in 3 months

pull request commentalexforencich/verilog-axis

FIFO reset

I think I can see what the issue is now. However, I explicitly did not reset that register so that there would be no issues with merging it into block RAM instances. Adding a reset could prevent proper inference of the block RAM. I would have to do quite a bit of reading and/or synthesis testing for various targets to figure out if adding that reset is acceptable. What I can look in to, however, is disabling the tready input for one cycle after reset is released.

LeChuck42

comment created time in 3 months

push eventalexforencich/verilog-axis

Alex Forencich

commit sha a7689b67725c8fe7b72d95b2a71d9b1f5ed8a8d0

Pipeline RAM output in RAM switch

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issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

It seems that it does not simulate correctly.

This is not a surprise. Anyway, the @alwaysparameters are not good. .negedgeshould not be used here. At least for `RESETn'. I still think the way to go is to fix the simulation.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@NicoPy

I have not checked if it simulates correctly.

It seems that it does not simulate correctly. Maybe among other things, some combinatorial processes are not being informed correctly about signals that are written in this sequential process. Also: Not sure, if there is a difference between Python2 and Python3 (worse in Python3).

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@LarsRlrs Yes. I was showing the way it is intended to be used (from my understanding).

Another code that suits your requirements is the following :

    @always(clk.posedge, RESETn.negedge)
    def seq():
        if clk.posedge :
            out1.next=in1 or in2
            out2.next=in1 and in2
        
        if RESETn == 0:
            out1.next=0
        else :
            pass

MyHDL complains there is no else ? Well... just add an else ;)

However, the conversion result is surprising :

INC_SEQ: process (clk, RESETn) is
begin
    if rising_edge(clk) then
        out1 <= stdl(bool(in1) or bool(in2));
        out2 <= stdl(bool(in1) and bool(in2));
    end if;
    if (RESETn = '0') then
        out1 <= '0';
    elsif rising_edge(clk) then
        null;
    end if;
end process INC_SEQ;

I have not checked if it simulates correctly.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@NicoPy Just one comment: The code that you wrote, makes out2 dependent from RESETn.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@LarsRlrs From what I understand, @always intended use is like this :

    @always(clk, RESETn)
    def seq():
        if RESETn == 0:
            out1.next=0
        elif clk.posedge :
            out1.next=in1 or in2
            out2.next=in1 and in2

    return instances()

You will notice there is an else ;) It translates to the following :

INC_SEQ: process (clk, RESETn) is
begin
    if (RESETn = '0') then
        out1 <= '0';
    elsif rising_edge(clk) then
        out1 <= stdl(bool(in1) or bool(in2));
        out2 <= stdl(bool(in1) and bool(in2));
    end if;
end process INC_SEQ;

For a reset at the end of the process, your version1 converts correctly but does not simulate. Maybe this is the way to go and try to make simulation work corectly.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

Probably, but I wonder what priority it will get and who is going to make the PR.

Hopefully, it is easy and not much effort to fix.

Xilinx also recommends synchronous resets?

Yes. But I can't do that at the moment.

And then you have the 3-process approach. I don't find that it increases the (source) code size that much. And it does not increase resource usage - win some, lose some.

I'd say, up to 50% and beyond is significant. Starting with one processes, you need one additional combinatorial signal for every interaction between functionality that is then separated into two sequential processes. Multiple interactions per state and a couple of states et voila: "ldlq", "ldlqw", "sellqw" (https://gist.github.com/josyb/efec12907bb82a06e42758c039767c7f). Much more for modules with a couple of counters and ShiftRegs.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

Could this be fixed so that mhdl-conversion does not insist on the else-clause of the Reset but uses the stuff before the Reset for rising clock edge?

Probably, but I wonder what priority it will get and who is going to make the PR.

The FPGA vendor Xilinx recommends to reset as few FFs as possible.

Xilinx also recommends synchronous resets?

But it really increases the code size. I would have to use an additional combinatorial process because two sequential processes alone will not do (additional clock cycle from one sequential process to the other).

And then you have the 3-process approach. I don't find that it increases the (source) code size that much. And it does not increase resource usage - win some, lose some.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@josyb

Does your desired construct synthesize?

Yes.

In all literature the standard VHDL asynchronous reset follows

The same literature that states one shall use Python for HDL? ;) It took until VHDL-2019 for VHDL to include interfaces. Writing the reset at the end is much older than 2017. We are not waiting for the literature :)

Again, MyHDL != Verilog. IMO the only way is to use two processes; one with a (either synchronous or asynchronous) reset and the second without.

Verilog synchronous: works Verilog asynchronous: works VHDL synchronous: works VHDL asynchronous: does not work

Could this be fixed so that mhdl-conversion does not insist on the else-clause of the Reset but uses the stuff before the Reset for rising clock edge?

The @always_seq construct was specifically added to simplify the choice of reset signal (active high or low; synchronous or asynchronous; or simply None) without having to update the MyHDL code depending on which FPGA vendor is targeted.

The FPGA vendor Xilinx recommends to reset as few FFs as possible.

I understand that this conflicts with the one-process state machine approach.

Your recommendation to use more than one process is cleaner from a design guide perspective and this almost makes me want to rewrite code. But it really increases the code size. I would have to use an additional combinatorial process because two sequential processes alone will not do (additional clock cycle from one sequential process to the other).

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

Does your desired construct synthesize? In all literature the standard VHDL asynchronous reset follows this template:

process (Clock, Reset)
begin
  if Reset = '0' then
    -- reset register, Q <= 0
  elsif RISING_EDGE(Clock) then
    -- increment register, Q <= Q + 1;
  end if;
end process;

Again, MyHDL != Verilog. IMO the only way is to use two processes; one with a (either synchronous or asynchronous) reset and the second without. The @always_seq construct was specifically added to simplify the choice of reset signal (active high or low; synchronous or asynchronous; or simply None) without having to update the MyHDL code depending on which FPGA vendor is targeted. I understand that this conflicts with the one-process state machine approach.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@NicoPy The version1 conversion result is the output that I expect to have. But the version1 myhdl code does not simulate correctly. It seems that this is executed twice for each clk rising edge.

It is my understanding that the notation in myhdl should include @always(clk.posedge), but I found no way to get to the expected VHDL conversion result with this. The reason seems to be that myhdl-conversion is searching for an else to the if RESETn==0, but there is no else and so myhdl-conversion raises an error.

    @always(clk.posedge, RESETn.negedge)
    def seq():
        out1.next=in1 or in2
        out2.next=in1 and in2
        
        if RESETn==0:
            out1.next=0

leads to No separate else clause found And

    @always(clk.posedge, RESETn)
    def seq():
        out1.next=in1 or in2
        out2.next=in1 and in2
        
        if RESETn==0:
            out1.next=0

leads to base type error in sensitivity list VHDL conversion result for synchronous reset is working. VHDL conversion result for asynchronous reset is not worling.

Again, here is the expected/desired conversion result (VHDL with asynchronous reset, but not every FF):


architecture MyHDL of inc is
begin

INC_SEQ: process (clk, RESETn) is
begin
    if rising_edge(clk) then
        out1 <= stdl(bool(in1) or bool(in2));
        out2 <= stdl(bool(in1) and bool(in2));
    end if;
    if (RESETn = '0') then
        out1 <= '0';
    end if;
end process INC_SEQ;

end architecture MyHDL;
LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@LarsRlrs That's what you get. But what is the output you expect to have?

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

Version1:

from myhdl import *
@block
def inc(clk, RESETn, in1, in2, out1, out2):
    @always(clk,RESETn)
    def seq():
        if clk.posedge:
            out1.next=in1 or in2
            out2.next=in1 and in2      
        if RESETn==0:
            out1.next=0
    return instances()

def convert_inc():
    clk=Signal(bool(0))
    RESETn=Signal(bool(0))
    
    in1,in2,out1,out2=[Signal(bool(0)) for k in range(4)]
    inc_1 = inc(clk, RESETn, in1, in2, out1, out2)

    inc_1.convert('VHDL')

Version 1 conversion (conversion result is as expected but does not simulate correctly in myhdl):

architecture MyHDL of inc is
begin

INC_SEQ: process (clk, RESETn) is
begin
    if rising_edge(clk) then
        out1 <= stdl(bool(in1) or bool(in2));
        out2 <= stdl(bool(in1) and bool(in2));
    end if;
    if (RESETn = '0') then
        out1 <= '0';
    end if;
end process INC_SEQ;

end architecture MyHDL;

Version 2:

from myhdl import *
@block
def inc(clk, RESETn, in1, in2, out1, out2):
    @always(clk,RESETn)
    def seq():
        if bool(clk.posedge) and clk==1:
            out1.next=in1 or in2
            out2.next=in1 and in2      
        if RESETn==0:
            out1.next=0
    return instances()

def convert_inc():
    clk=Signal(bool(0))
    RESETn=Signal(bool(0))
    
    in1,in2,out1,out2=[Signal(bool(0)) for k in range(4)]
    inc_1 = inc(clk, RESETn, in1, in2, out1, out2)

    inc_1.convert('VHDL')

Version 2 conversion (simulation seems to be ok but conversion is not ok; synthesis will use CE):

architecture MyHDL of inc is
begin

INC_SEQ: process (clk, RESETn) is
begin
    if (rising_edge(clk) and (clk = '1')) then
        out1 <= stdl(bool(in1) or bool(in2));
        out2 <= stdl(bool(in1) and bool(in2));
    end if;
    if (RESETn = '0') then
        out1 <= '0';
    end if;
end process INC_SEQ;

end architecture MyHDL;

Anything with @always(clk.posedge....) makes things worse.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

@LarsRlrs Can you provide the resulting VHDL code you expect ? Please embed the code in the body of your message (using markdown code tag), not in an external file. It will be much easier to read this thread.

LarsRlrs

comment created time in 3 months

issue commentmyhdl/myhdl

Asynchronous Reset but not every FF, VHDL

My understanding is that myhdl is supposed to increase freedom and possibilities. Yes, but MyHDL is not Verilog in disguise -- although one might think so because of the @always decorators.

LarsRlrs

comment created time in 3 months

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