Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
OpenTitan: Open source silicon root of trust
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
A dependency management tool for hardware projects.
Functional verification project for the CORE-V family of RISC-V cores.
SweRV EH1 core
FuseSoC-based SoC for SweRV EH1
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
An abstraction library for interfacing EDA tools