danielmlynek/ibex 0

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

danielmlynek/opentitan 0

OpenTitan: Open source silicon root of trust

dawidzim/axi 0

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

dawidzim/bender 0

A dependency management tool for hardware projects.

dawidzim/core-v-verif 0

Functional verification project for the CORE-V family of RISC-V cores.

dawidzim/Cores-SweRV 0

SweRV EH1 core

dawidzim/Cores-SweRVolf 0

FuseSoC-based SoC for SweRV EH1

dawidzim/cv32e40p 0

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

dawidzim/edalize 0

An abstraction library for interfacing EDA tools