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Andrew Lenharth darthscsi SiFive

darthscsi/circt 0

Circuit IR Compilers and Tools

darthscsi/FSR_Endstop 0

Force-Sensitive Resistor controller designed for Delta 3D printers for automatic bed leveling

darthscsi/Marlin 0

Reprap FW with look ahead. SDcard and LCD support. It works on Gen6, Ultimaker, RAMPS and Sanguinololu

darthscsi/RepRapFirmware 0

OO C++ RepRap Firmware

darthscsi/Smoothieware 0

Modular, opensource, high performance G-code interpreter and CNC controller written in Object-Oriented C++

pull request commentllvm/circt

[FIRRTL] Add Optional Symbol to InstanceOp

This is what we are doing in sv, but I'm hesitant to do it in firrtl. Namely, we have structures which index by name already and need to index ports. We can add symbols to everything (sv-like), or we can use module::name + don't touch. just instance symbols would make NLAs nicer, though the final name would still be a string since ports and wires and nodes don't have symbols.

Instances are interesting enough I can see the utility of the symbol. Another option to generate a symbol would be an NLA targeting the name (~circ|Mod>inst, or whatever). That also gives you a way to generate a symbol for an arbitrary name in firrtl and keep a unified set of naming constructs.

seldridge

comment created time in 4 minutes

Pull request review commentllvm/circt

[FIRRTL] Add support for multi-bit FIRRTL Memory mask type, NFC

 MemOp::PortKind MemOp::getPortKind(size_t resultNo) {       getResult(resultNo).getType().cast<FIRRTLType>()); } +/// Return the number of bits in the mask for the memory.+size_t MemOp::getMaskBits() {+  assert(getNumResults() != 0 && "Mems with no read/write ports are illegal");

should be handled in verification.

prithayan

comment created time in 9 minutes

Pull request review commentllvm/circt

[FIRRTL] Add support for multi-bit FIRRTL Memory mask type, NFC

 MemOp::PortKind MemOp::getPortKind(size_t resultNo) {       getResult(resultNo).getType().cast<FIRRTLType>()); } +/// Return the number of bits in the mask for the memory.+size_t MemOp::getMaskBits() {+  assert(getNumResults() != 0 && "Mems with no read/write ports are illegal");++  for (auto res : getResults()) {+    auto firstPortType = res.getType().cast<FIRRTLType>();+    if (getMemPortKindFromType(firstPortType) == PortKind::Read)+      continue;++    FIRRTLType mType;+    for (auto t :+         firstPortType.getPassiveType().cast<BundleType>().getElements()) {+      if (t.name.getValue().contains("mask"))+        mType = t.type;+    }+    if (mType.dyn_cast_or_null<UIntType>())+      return mType.getBitWidthOrSentinel();+  }+  // Default is 1 bit.+  return 1;

should the default be 0?

prithayan

comment created time in 9 minutes

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Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitStmt(WhenOp op) {   lowerBlock(&op.getElseBlock()); } +// Convert an aggregate type into a flat list of fields.  This is used+// when working with instances and mems to flatten them.+static void flattenType(FIRRTLType type, SmallVectorImpl<FIRRTLType> &results) {+  std::function<void(FIRRTLType)> flatten = [&](FIRRTLType type) {+    TypeSwitch<FIRRTLType>(type)+        .Case<BundleType>([&](auto bundle) {+          for (auto &elt : bundle.getElements())+            flatten(elt.type);+          return;+        })+        .Case<FVectorType>([&](auto vector) {+          for (size_t i = 0, e = vector.getNumElements(); i != e; ++i)+            flatten(vector.getElementType());+          return;+        })+        .Default([&](auto) {+          results.push_back({type});+          return;+        });+  };+  return flatten(type);+}++// Create subfield and subaccess to access all the leaf elements of the result+// of the input op and insert the results into the flatData.+void TypeLoweringVisitor::crerateAggregateAccess(+    SubfieldOp op, SmallVectorImpl<Value> &flatData) {+  std::function<void(Value val)> flatten = [&](Value val) {+    TypeSwitch<FIRRTLType>(val.getType().cast<FIRRTLType>())+        .Case<BundleType>([&](BundleType bundle) {+          for (auto &elt : llvm::enumerate(bundle.getElements())) {+            auto subF = builder->create<SubfieldOp>(val, elt.index());+            flatten(subF.getResult());+          }+          return;+        })+        .Case<FVectorType>([&](auto vector) {+          for (size_t i = 0, e = vector.getNumElements(); i != e; ++i) {+            auto subF = builder->create<SubindexOp>(val, i);+            flatten(subF.getResult());+          }+          return;+        })+        .Default([&](auto) {+          flatData.push_back(val);+          return;+        });+  };+  return flatten(op.getResult());+}++/// Map the flattened memory ports to the original memory.+void TypeLoweringVisitor::flattenMem(SubfieldOp oldField, StringRef name,+                                     SmallVectorImpl<unsigned> &maskBits,+                                     Value newMemRes, unsigned fieldIndex,+                                     bool isRead) {+  SmallVector<Value, 8> flatData;+  crerateAggregateAccess(oldField, flatData);+  if (name == "mask" || name == "wmask") {+    SmallVector<Value, 8> tmp;+    for (auto maskB : llvm::enumerate(maskBits)) {+      auto m = flatData[maskB.index()];+      for (unsigned repeat = 0; repeat < maskB.value(); ++repeat)+        tmp.push_back(m);+    }+    flatData = tmp;+  }+  auto newData = getSubWhatever(newMemRes, fieldIndex);+  size_t uptoBits = 0;+  WireOp lastIndexWire;++  for (auto fData : flatData) {+    auto fieldBits = fData.getType().cast<FIRRTLType>().getBitWidthOrSentinel();

Can this all be simplified with a struct/vector -> int cast instead?

prithayan

comment created time in 14 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitDecl(MemOp op) {     oldPorts.push_back(wire);     result.replaceAllUsesWith(wire.getResult());   }+  SmallVector<FIRRTLType> flatMemType;+  size_t maskGran = 1;+  SmallVector<unsigned> maskBits;+  if (flattenAggregateMemData) {+    SmallVector<Operation *, 8> flatData;+    flattenType(op.getDataType(), flatMemType);+    SmallVector<int32_t> memWidths;+    for (auto f : flatMemType) {+      memWidths.push_back(f.getBitWidthOrSentinel());+    }+    // MaskGranularity : how many bits each mask bit controls.+    maskGran = memWidths[0];+    size_t memFlatWidth = 0;+    for (auto w : memWidths) {+      memFlatWidth += w;+      maskGran = llvm::GreatestCommonDivisor64(maskGran, w);+    }+    uint32_t totalMaskBits = 0;+    for (auto w : memWidths) {+      maskBits.push_back(w / maskGran);+      totalMaskBits += w / maskGran;+    }+    SmallVector<Type, 8> ports;+    SmallVector<Attribute, 8> portNames;++    auto flatType =+        IntType::get(context, op.getDataType().isSignedInteger(), memFlatWidth);+    auto opPorts = op.getPorts();+    for (size_t portIdx = 0, e = opPorts.size(); portIdx < e; ++portIdx) {+      auto port = opPorts[portIdx];+      ports.push_back(MemOp::getTypeForPort(op.depth(), flatType, port.second,

can't you use cloneMemWithNewType?

prithayan

comment created time in 21 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 firrtl.circuit "TopLevel" {     // CHECK-NEXT: firrtl.connect %[[WIRE_A_W_DATA]], %wData_a     // CHECK-NEXT: firrtl.connect %[[WIRE_B_W_DATA]], %wData_b +    // ---------------------------------------------------------------------------------+    // If flatten memory data is enabled+    // FLATTEN: %memory_r, %memory_w = firrtl.mem Undefined  {depth = 16 : i64, name = "memory", portNames = ["r", "w"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<16>>, !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<16>, mask: uint<2>>+      // FLATTEN: %0 = firrtl.subfield %memory_r(0) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<16>>) -> !firrtl.uint<4>+      // FLATTEN: firrtl.connect %0, %memory_r_addr : !firrtl.uint<4>, !firrtl.uint<4>+      // FLATTEN: %1 = firrtl.subfield %memory_r(1) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<16>>) -> !firrtl.uint<1>+      // FLATTEN: firrtl.connect %1, %memory_r_en : !firrtl.uint<1>, !firrtl.uint<1>+      // FLATTEN: %2 = firrtl.subfield %memory_r(2) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<16>>) -> !firrtl.clock+      // FLATTEN: firrtl.connect %2, %memory_r_clk : !firrtl.clock, !firrtl.clock+      // FLATTEN: %3 = firrtl.subfield %memory_r(3) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<16>>) -> !firrtl.uint<16>+    //+    // ---------------------------------------------------------------------------------+    // Read ports+    // FLATTEN:  %4 = firrtl.bits %3 7 to 0 : (!firrtl.uint<16>) -> !firrtl.uint<8>+    // FLATTEN:  firrtl.connect %[[memory_r_data_a:.+]], %4 : !firrtl.uint<8>, !firrtl.uint<8>+    // FLATTEN:  %5 = firrtl.bits %3 15 to 8 : (!firrtl.uint<16>) -> !firrtl.uint<8>+    // FLATTEN:  firrtl.connect %[[memory_r_data_b:.+]], %5 : !firrtl.uint<8>, !firrtl.uint<8>+    // --------------------------------------------------------------------------------+    // Write Ports+    // FLATTEN:  %9 = firrtl.subfield %memory_w(3)+    // FLATTEN:  %10 = firrtl.wire  : !firrtl.uint<8>+    // FLATTEN:  firrtl.connect %10, %[[memory_w_data_a:.+]] : !firrtl.uint<8>, !firrtl.uint<8>+    // FLATTEN:  %11 = firrtl.cat %[[memory_w_data_b:.+]], %10+    // FLATTEN:  %12 = firrtl.wire+    // FLATTEN:  firrtl.connect %12, %11+    // FLATTEN:  firrtl.connect %9, %12+    //+    // --------------------------------------------------------------------------------+    // Mask Ports+    //  FLATTEN: %13 = firrtl.subfield %memory_w(4)+    //  FLATTEN: %14 = firrtl.wire  : !firrtl.uint<1>+    //  FLATTEN: firrtl.connect %14, %[[memory_w_mask_a:.+]] : !firrtl.uint<1>, !firrtl.uint<1>+    //  FLATTEN: %15 = firrtl.cat %[[memory_w_mask_b:.+]], %14 : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<2>+    //  FLATTEN: %16 = firrtl.wire  : !firrtl.uint<2>+    //  FLATTEN: firrtl.connect %16, %15 : !firrtl.uint<2>, !firrtl.uint<2>+    //  FLATTEN: firrtl.connect %13, %16 : !firrtl.uint<2>, !firrtl.uint<2>+    // Connections to module ports+    // FLATTEN:  firrtl.connect %rData_a, %[[memory_r_data_a]] : !firrtl.uint<8>, !firrtl.uint<8>+    // FLATTEN:  firrtl.connect %rData_b, %[[memory_r_data_b]] : !firrtl.uint<8>, !firrtl.uint<8>+    // FLATTEN:  firrtl.connect %[[memory_w_mask_a]], %wMask_a : !firrtl.uint<1>, !firrtl.uint<1>

For the bundle case, you need to test unequal sides. uint<8>, uint<16>.

prithayan

comment created time in 32 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitStmt(WhenOp op) {   lowerBlock(&op.getElseBlock()); } +// Convert an aggregate type into a flat list of fields.  This is used+// when working with instances and mems to flatten them.+static void flattenType(FIRRTLType type, SmallVectorImpl<FIRRTLType> &results) {+  std::function<void(FIRRTLType)> flatten = [&](FIRRTLType type) {+    TypeSwitch<FIRRTLType>(type)+        .Case<BundleType>([&](auto bundle) {+          for (auto &elt : bundle.getElements())+            flatten(elt.type);+          return;+        })+        .Case<FVectorType>([&](auto vector) {+          for (size_t i = 0, e = vector.getNumElements(); i != e; ++i)+            flatten(vector.getElementType());+          return;+        })+        .Default([&](auto) {+          results.push_back({type});+          return;+        });+  };+  return flatten(type);+}++// Create subfield and subaccess to access all the leaf elements of the result+// of the input op and insert the results into the flatData.+void TypeLoweringVisitor::crerateAggregateAccess(

return smallvector by value.

prithayan

comment created time in 17 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitStmt(WhenOp op) {   lowerBlock(&op.getElseBlock()); } +// Convert an aggregate type into a flat list of fields.  This is used+// when working with instances and mems to flatten them.+static void flattenType(FIRRTLType type, SmallVectorImpl<FIRRTLType> &results) {+  std::function<void(FIRRTLType)> flatten = [&](FIRRTLType type) {+    TypeSwitch<FIRRTLType>(type)+        .Case<BundleType>([&](auto bundle) {+          for (auto &elt : bundle.getElements())+            flatten(elt.type);+          return;+        })+        .Case<FVectorType>([&](auto vector) {+          for (size_t i = 0, e = vector.getNumElements(); i != e; ++i)+            flatten(vector.getElementType());+          return;+        })+        .Default([&](auto) {+          results.push_back({type});+          return;+        });+  };+  return flatten(type);+}++// Create subfield and subaccess to access all the leaf elements of the result+// of the input op and insert the results into the flatData.+void TypeLoweringVisitor::crerateAggregateAccess(+    SubfieldOp op, SmallVectorImpl<Value> &flatData) {+  std::function<void(Value val)> flatten = [&](Value val) {+    TypeSwitch<FIRRTLType>(val.getType().cast<FIRRTLType>())+        .Case<BundleType>([&](BundleType bundle) {+          for (auto &elt : llvm::enumerate(bundle.getElements())) {+            auto subF = builder->create<SubfieldOp>(val, elt.index());+            flatten(subF.getResult());+          }+          return;+        })+        .Case<FVectorType>([&](auto vector) {+          for (size_t i = 0, e = vector.getNumElements(); i != e; ++i) {+            auto subF = builder->create<SubindexOp>(val, i);+            flatten(subF.getResult());+          }+          return;+        })+        .Default([&](auto) {+          flatData.push_back(val);+          return;+        });+  };+  return flatten(op.getResult());+}++/// Map the flattened memory ports to the original memory.+void TypeLoweringVisitor::flattenMem(SubfieldOp oldField, StringRef name,

rename? The comment and the function name don't align well.

prithayan

comment created time in 18 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 MemOp::PortKind MemOp::getPortKind(size_t resultNo) {       getResult(resultNo).getType().cast<FIRRTLType>()); } +/// Return the number of bits in the mask for the memory.+size_t MemOp::getMaskBits() {+  assert(getNumResults() != 0 && "Mems with no read/write ports are illegal");

And it seems what you really want to know is if there are no write ports.

prithayan

comment created time in 38 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitDecl(MemOp op) {       // go both directions, depending on the port direction.       if (name == "data" || name == "mask" || name == "wdata" ||           name == "wmask" || name == "rdata") {-        for (auto field : fields) {-          auto realOldField = getSubWhatever(oldField, field.index);-          auto newField = getSubWhatever(-              newMemories[field.index].getResult(index), fieldIndex);-          if (rType.getElement(fieldIndex).isFlip)-            std::swap(realOldField, newField);-          builder->create<ConnectOp>(newField, realOldField);+        bool isRead = rType.getElement(fieldIndex).isFlip;

isRead can be sunk into the if.

prithayan

comment created time in 19 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitDecl(MemOp op) {     oldPorts.push_back(wire);     result.replaceAllUsesWith(wire.getResult());   }+  SmallVector<FIRRTLType> flatMemType;+  size_t maskGran = 1;+  SmallVector<unsigned> maskBits;

These seem only used inside the if.

prithayan

comment created time in 24 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 MemOp::PortKind MemOp::getPortKind(size_t resultNo) {       getResult(resultNo).getType().cast<FIRRTLType>()); } +/// Return the number of bits in the mask for the memory.+size_t MemOp::getMaskBits() {+  assert(getNumResults() != 0 && "Mems with no read/write ports are illegal");

this should be in verification. Especially since this function won't catastrophically fail with 0 results.

prithayan

comment created time in 42 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 MemOp::PortKind MemOp::getPortKind(size_t resultNo) {       getResult(resultNo).getType().cast<FIRRTLType>()); } +/// Return the number of bits in the mask for the memory.+size_t MemOp::getMaskBits() {+  assert(getNumResults() != 0 && "Mems with no read/write ports are illegal");++  for (auto res : getResults()) {+    auto firstPortType = res.getType().cast<FIRRTLType>();+    if (getMemPortKindFromType(firstPortType) == PortKind::Read)+      continue;++    FIRRTLType mType;+    for (auto t :+         firstPortType.getPassiveType().cast<BundleType>().getElements()) {+      if (t.name.getValue().contains("mask"))+        mType = t.type;+    }+    if (mType.dyn_cast_or_null<UIntType>())

Isn't this required for a write port? I.E. it should never fail.

prithayan

comment created time in 38 minutes

Pull request review commentllvm/circt

[FIRRTL] Create a single FIRRTL memory from an aggregate data type

 void TypeLoweringVisitor::visitDecl(MemOp op) {     oldPorts.push_back(wire);     result.replaceAllUsesWith(wire.getResult());   }+  SmallVector<FIRRTLType> flatMemType;+  size_t maskGran = 1;+  SmallVector<unsigned> maskBits;+  if (flattenAggregateMemData) {+    SmallVector<Operation *, 8> flatData;+    flattenType(op.getDataType(), flatMemType);+    SmallVector<int32_t> memWidths;+    for (auto f : flatMemType) {+      memWidths.push_back(f.getBitWidthOrSentinel());

You should never see a memory with a type which returns a sentinel. Let getBitWidth fail, rather than allowing -1 widths.

prithayan

comment created time in 22 minutes

PullRequestReviewEvent

Pull request review commentllvm/circt

[FIRRTL] add all-in-one metadata pass

+//===- EmitMetadata.cpp - Emit various types of metadata --------*- C++ -*-===//+//+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.+// See https://llvm.org/LICENSE.txt for license information.+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception+//+//===----------------------------------------------------------------------===//+//+// This file defines the EmitMetadata pass.+//+//===----------------------------------------------------------------------===//++#include "PassDetails.h"+#include "circt/Dialect/FIRRTL/FIRRTLAnnotations.h"+#include "circt/Dialect/FIRRTL/FIRRTLOps.h"+#include "circt/Dialect/FIRRTL/FIRRTLTypes.h"+#include "circt/Dialect/FIRRTL/Passes.h"+#include "circt/Dialect/HW/HWAttributes.h"+#include "circt/Dialect/SV/SVOps.h"+#include "llvm/ADT/STLExtras.h"+#include "llvm/Support/JSON.h"++using namespace circt;+using namespace firrtl;++namespace {+class EmitMetadataPass : public EmitMetadataBase<EmitMetadataPass> {+  LogicalResult emitRetimeModulesMetadata();+  void getDependentDialects(mlir::DialectRegistry &registry) const override;+  void runOnOperation() override;+};+} // end anonymous namespace++/// This pass collects the name of each module annotated and prints them all as+/// a JSON array.+LogicalResult EmitMetadataPass::emitRetimeModulesMetadata() {++  // Circuit level annotation.+  auto *retimeModulesAnnoClass =+      "sifive.enterprise.firrtl.RetimeModulesAnnotation";+  // Per module annotation.+  auto *retimeModuleAnnoClass =+      "sifive.enterprise.firrtl.RetimeModuleAnnotation";

literal strings will be constant data, and will be merged. hoisting them explicitly is for readability. If they are only used in this function, then I wouldn't worry about it.

youngar

comment created time in an hour

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push eventllvm/circt

Andrew Lenharth

commit sha 312a65e9c51f569149495dbfabf07f608262ab0a

[NFC] Improve discoverability of formatting flags closes #1867

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issue closedllvm/circt

Lowering options are undiscoverable

--lowering-options for firtool is opaque. We need help text at least listing the valid options.

closed time in a day

darthscsi

issue openedllvm/circt

Lowering options are undiscoverable

--lowering-options for firtool is opaque. We need help text at least listing the valid options.

created time in a day

issue closedllvm/circt

[FIRRTL] BlackBoxInlineAnno file path

Annotation:

    "class":"firrtl.transforms.BlackBoxInlineAnno",
    "target":"CoreIPSubsystemVerifTestHarness.DummyVroom",

Needs to pay attention to:

    "class":"sifive.enterprise.firrtl.TestBenchDirAnnotation",

to place files in correct directory

closed time in a day

darthscsi

issue commentllvm/circt

[FIRRTL] BlackBoxInlineAnno file path

looks like a general difference in output location, SFC is adding directories which firtool isn't. This probably can be handled in build scripts.

darthscsi

comment created time in a day

push eventllvm/circt

Andrew Lenharth

commit sha c4ac7b8fb566ac95530154baeacaf5368ba0a11c

Annotation Scattering and trivial processing Pass (#1808) Add a pass to handle all annotation scattering. This pass is table driven, with customizable scattering per-annotation-class. When this is fleshed out, it will replace the annotation handling code in the parser. Right now, this supports a couple testing annotation to make test cases against. Until this is live in the pipelines, add an option to the parser to bypass annotation handling and scattering to enable testing.

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PR merged llvm/circt

Annotation Scattering and trivial processing Pass

Add a pass to handle all annotation scattering. This pass is table driven, with customizable scattering per-annotation-class. When this is fleshed out, it will replace the annotation handling code in the parser.

Right now, this supports a couple testing annotation to make test cases against.

Until this is live in the pipelines, add an option to the parser to bypass annotation handling and scattering to enable testing.

+980 -123

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13 changed files

darthscsi

pr closed time in 2 days

Pull request review commentllvm/circt

Annotation Scattering and trivial processing Pass

 struct FIRCircuitParser : public FIRParser { };  } // end anonymous namespace+ParseResult+FIRCircuitParser::importAnnotationsRaw(SMLoc loc, StringRef circuitTarget,+                                       StringRef annotationsStr,+                                       SmallVector<Attribute> &attrs) {++  auto annotations = json::parse(annotationsStr);+  if (auto err = annotations.takeError()) {+    handleAllErrors(std::move(err), [&](const json::ParseError &a) {+      auto diag = emitError(loc, "Failed to parse JSON Annotations");+      diag.attachNote() << a.message();+    });+    return failure();+  }++  json::Path::Root root;+  llvm::StringMap<ArrayAttr> thisAnnotationMap;+  if (!fromJSONRaw(annotations.get(), circuitTarget, attrs, root,+                   getContext())) {+    auto diag = emitError(loc, "Invalid/unsupported annotation format");+    std::string jsonErrorMessage =+        "See inline comments for problem area in JSON:\n";+    llvm::raw_string_ostream s(jsonErrorMessage);+    root.printErrorContext(annotations.get(), s);+    diag.attachNote() << jsonErrorMessage;+    return failure();+  }++  return success();+}

The code should be temporary and should cease existing once the transition happens.

darthscsi

comment created time in 2 days

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