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SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

https://github.com/SpinalHDL/VexRiscv

SpinalHDL

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contributors (According to the first 100)

Dolu1990
lindemer
tomverbeure
Pradeep2004
mateusz-holenko
mithro
sebastien-riou
xobs
zeldin
japm48
rdolbeau
bunnie
alexismarquet
cutephoton
Wallbraker
JohnDMcMaster
MarekPikula
rpls
Snoopy87
tcal-x
kaofishy
banahogg