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anycore/anycore-riscv-src 10

The RTL source for AnyCore RISC-V

kwonalbert/oram 10

Recursive unified ORAM

anycore/anycore-riscv-tests 3

A small suite of tests for AnyCore RISC-V

Jbalkind/Amazon-Hackathon 3

March 30th-31st 2012

Jbalkind/openpiton 2

The OpenPiton Platform

Jbalkind/herdtools 1

diy testing tool for weak memory models, herd design

dpetrisko/openpiton 0

The OpenPiton Platform

Jbalkind/ao486 0

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.

Jbalkind/ao486_MiSTer 0

ao486 port for MiSTer

issue closedPrincetonUniversity/openpiton

JTAG debug

"The FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module." But how can I make sure which GPIO would be used? It seems the FPGA_TMS, FPGA_TDI, FPGA_TDO, FPGA_TCK are not used as GPIO.

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hikerxx50111

issue openedPrincetonUniversity/openpiton

JTAG debug

"The FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module." But how can I make sure which GPIO would be used? It seems the FPGA_TMS, FPGA_TDI, FPGA_TDO, FPGA_TCK are not used as GPIO.

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pull request commentPrincetonUniversity/openpiton

Fix LR. Prevent it from changing mshr_st_state

Booting dual core linux on FPGA. Verified both with Ariane and Black-parrot.

fei-g

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PR opened PrincetonUniversity/openpiton

Fix LR. Prevent it from changing mshr_st_state

LR changes the st_state to WAIT_ACK as a flag to mark the future data ack to be ACKDT_LR. But that will overwrite the current st_state set by previous store, which leads to a freeze in L15. This issue was triggered when integrating black parrot. (This is not a issue when working with Ariane though, because Ariane will wait for all outstanding stores to finish before it sends LR)

Fix is easy. Because we actually don't need to rely on st_state to recognize ACKDT_LR. Changing the order of conditions will separate ACKDT_LR from ACKDT_ST_XX.

+4 -8

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A wrapper for the SPEC CPU2006 benchmark suite.

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Ghidra is a software reverse engineering (SRE) framework

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issue commentPrincetonUniversity/openpiton

SD card issue on VCU118

@leon575777642 @Jbalkind

So I was finally able to get the SD card boot working. I kept everything timing wise unchanged. There was a post on Xilinx forums that said to set the VADJ through the System Controller UI program to 1.2V. After changing that, and enabling the SCUI on SW16, I'm able to reliably boot from the SD card.

Thank you to both of you for the help.

shirlynan

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