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orbcode/orbuculum 216

Cortex M SWO SWV Demux and Postprocess

litex-hub/litespi 22

Small footprint and configurable SPI core

orbcode/orbtrace 13

Debug and parallel trace hardware for CORTEX-M

orbcode/orbtrace_hw 1

Orbtrace hardware

zyp/blackmagic 0

In application debugger for ARM Cortex microcontrollers.

zyp/exclave 0

Exclave embedded service runner

zyp/hbmqtt 0

MQTT client/broker using Python asynchronous I/O

zyp/libopencm3 0

Open Source ARM cortex m microcontroller library

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Vegard Storheil Eriksen

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dfu: Add multiple flash areas.

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Vegard Storheil Eriksen

commit sha 73c48dcb63e0ec2d260ae224cb45558187df877c

leds: Add CSR for software control of LEDs.

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Vegard Storheil Eriksen

commit sha 9e9f09e575034ea278563ee1c64f999dc66eea87

test: Add registers for testing IO signals.

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Vegard Storheil Eriksen

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usb: Add iSerialNumber handler based on flash UID.

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Vegard Storheil Eriksen

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soc: Add bootloader-auto-reset option.

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Dave Marples

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Cleanup and move subdirectories to other repositories

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Dave Marples

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Fix CMSIS-DAP v1 support

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Vegard Storheil Eriksen

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Add profile presets to platforms for common configurations.

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Add profile presets to platforms for common configurations.

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PR opened trabucayre/openFPGALoader

progressBar: Use only stdout.

The progress markers of the progress bar were output to stderr while the rest was output to stdout.

This patch moves everything to stdout.

+2 -2

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Exclave embedded service runner

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MemberEvent

pull request commentlitex-hub/litespi

Litespi - using the ODDR/IDDR, simplifying models

The clkgen changes doesn't account for when the clock is output through the STARTUPE2 or USRMCLK primitives. I also seem to recall that the bottom bank on the ECP5 doesn't have DDR registers at all.

pawelsag

comment created time in a month

issue commentlitex-hub/litespi

Improve resources usage.

Out of curiosity, have you checked the resource usage with only the master module enabled, not MMAP?

enjoy-digital

comment created time in 2 months

issue commentlitex-hub/litespi

Improve resources usage.

I've been thinking that the PHY can be simplified a lot by removing the CMD and READ special casing and having LiteSPIMMAP use the USER interface instead. There doesn't seem to be any performance benefit in the special casing. While some of the resource usage would just move from the PHY core to the MMAP core, I believe the net total should be lower.

enjoy-digital

comment created time in 2 months

issue commentlitex-hub/litespi

How to write to flash

Oh, my bad, the line setting phyconfig got removed by accident when I cleaned up the code snippet above. I've added it back.

len, width and mask needs to be set to 8, 1 and 1 respectively.

navaneeth-cirel

comment created time in 2 months

issue commentlitex-hub/litespi

How to write to flash

What exactly is not working? Have you scoped the signals? Did you assert CS first?

navaneeth-cirel

comment created time in 2 months

issue commentlitex-hub/litespi

How to write to flash

LiteSPI doesn't have bitbang registers, @xobs code is for litex.soc.cores.spi_flash.

For LiteSPI you can use the registers provided by the LiteSPIMaster module for the same purpose. Here's an example of how to write flash from python over a wishbone bridge:

#!/usr/bin/env python3

import sys
import deps
from litex.tools.litex_client import RemoteClient

c = RemoteClient()
c.open()

PROGRAM_SIZE = 256
ERASE_SIZE = 4096

def transfer_byte(b):
    while not (c.regs.spiflash_mmap_master_status.read() & (1 << 0)):
        pass

    c.regs.spiflash_mmap_master_rxtx.write(b)

    while not (c.regs.spiflash_mmap_master_status.read() & (1 << 1)):
        pass

    return c.regs.spiflash_mmap_master_rxtx.read()

def transfer_cmd(bs):
    c.regs.spiflash_mmap_master_cs.write(1)

    r = [transfer_byte(b) for b in bs]

    c.regs.spiflash_mmap_master_cs.write(0)

    return bytes(r)

def read_status_register():
    return transfer_cmd(b'\x05\x00')[1]

def write_enable():
    transfer_cmd(b'\x06')

def page_program(addr, data):
    transfer_cmd(b'\x02' + addr.to_bytes(3, 'big') + data)

def sector_erase(addr):
    transfer_cmd(b'\x20' + addr.to_bytes(3, 'big'))

def write_stream(addr, stream):
    assert addr & (ERASE_SIZE - 1) == 0

    while True:
        data = stream.read(PROGRAM_SIZE)

        if not data:
            break
        
        if addr & (ERASE_SIZE - 1) == 0:
            write_enable()
            sector_erase(addr)

            while read_status_register() & 1:
                pass

            print(f'Erased addr {addr}.')

        write_enable()
        page_program(addr, data)

        while read_status_register() & 1:
            pass

        print(f'Wrote {len(data)} bytes.')

        addr += len(data)

def main():
    with open(sys.argv[1], 'rb') as f:
        write_stream(0, f)

if __name__ == '__main__':
    main()

If you want a faster option, I've written a flash writer module that just takes a data and address stream: https://github.com/orbcode/orbtrace/blob/main/orbtrace/flashwriter.py

navaneeth-cirel

comment created time in 2 months

pull request commentenjoy-digital/litex

ECP5PLL: implement 4-output solver

I don't think backwards compatibility for this is a big issue considering expose_dpa() were merged only two weeks ago in #949.

thirtythreeforty

comment created time in 3 months

pull request commentenjoy-digital/litex

ECP5PLL: implement 4-output solver

Sounds reasonable to me.

thirtythreeforty

comment created time in 3 months

Pull request review commentenjoy-digital/litex

ECP5PLL: implement 4-output solver

 # Lattice / ECP5 -----------------------------------------------------------------------------------  class ECP5PLL(Module):-    nclkouts_max    = 3+    nclkouts_max    = 4     clki_div_range  = (1, 128+1)     clkfb_div_range = (1, 128+1)     clko_div_range  = (1, 128+1)     clki_freq_range = (    8e6,  400e6)     clko_freq_range = (3.125e6,  400e6)     vco_freq_range  = (  400e6,  800e6)+    pfd_freq_range  = (   10e6,  400e6)

Ah, fair. Still seems a bit unintuitive that the minimum is higher for f_PFD than f_IN, considering the former is derived from the latter through a divisor.

I can also confirm that for my sample size of one, it works at 5 MHz in practice. :)

thirtythreeforty

comment created time in 3 months

PullRequestReviewEvent

pull request commentenjoy-digital/litex

ECP5PLL: implement 4-output solver

This looks good to me.

I was about to comment that the margin for the selected output should probably be set to 0 to keep any deviation from affecting other outputs before I realized that it doesn't factor into the calculation of the VCO frequency that the other outputs are derived from. Setting a large margin on outputs that doesn't need to be very specific would actually make it easier to find a valid feedback path.

One thing I'm a little bit concerned about is dynamic phase adjustment. The documentation states:

The clock output selected as the feedback cannot use the dynamic phase adjustment feature since it will cause the PLL to unlock. For example if the FB_MODE is INT_OP or CLKOP, then there should be no phase shift on CLKOP.

It'd be good to add a way to disallow specific outputs from being selected for the feedback path.

thirtythreeforty

comment created time in 3 months

Pull request review commentenjoy-digital/litex

ECP5PLL: implement 4-output solver

 # Lattice / ECP5 -----------------------------------------------------------------------------------  class ECP5PLL(Module):-    nclkouts_max    = 3+    nclkouts_max    = 4     clki_div_range  = (1, 128+1)     clkfb_div_range = (1, 128+1)     clko_div_range  = (1, 128+1)     clki_freq_range = (    8e6,  400e6)     clko_freq_range = (3.125e6,  400e6)     vco_freq_range  = (  400e6,  800e6)+    pfd_freq_range  = (   10e6,  400e6)

I believe the clki_freq_range above is supposed to be the same as this. They should probably be combined.

thirtythreeforty

comment created time in 3 months

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Vegard Storheil Eriksen

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Improve support for orbtrace_mini.

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Dave Marples

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Initial support for jtag

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Vegard Storheil Eriksen

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deps: Update deps.

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Vegard Storheil Eriksen

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platforms/orbtrace_mini: Add I2C.

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soc: Add SPI flash.

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usb: Add initial DFU support.

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Vegard Storheil Eriksen

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cmsis_dap: Fix JTAG support.

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Vegard Storheil Eriksen

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platforms/ecpix5: Add flash.

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Vegard Storheil Eriksen

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platforms/ecpix5: Add flash.

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Vegard Storheil Eriksen

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platforms/orbtrace_mini: Add I2C.

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Vegard Storheil Eriksen

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soc: Add SPI flash.

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usb: Add initial DFU support.

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cmsis_dap: Fix JTAG support.

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