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Merge pull request #24 from OpenXiangShan/replace Refine replacement

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refilldiff: disable by default

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mmu.tlb: set itlb's and l2tlb's size (#1014) * mmu.tlb: l2tlb's l3 now 128 sets and 4 ways * mmu.tlb: set itlb default size

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Yinan Xu

commit sha 88825c5cc17cb5e1df50964cd03c71974cc7730d

backend: support instruction fusion cases (#1011) This commit adds some simple instruction fusion cases in decode stage. Currently we only implement instruction pairs that can be fused into RV64GCB instructions. Instruction fusions are detected in the decode stage by FusionDecoder. The decoder checks every two instructions and marks the first instruction fused if they can be fused into one instruction. The second instruction is removed by setting the valid field to false. Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc. Currently, ftq in frontend needs every instruction to commit. However, the second instruction is removed from the pipeline and will not commit. To solve this issue, we temporarily add more bits to isFused to indicate the offset diff of the two fused instruction. There are four possibilities now. This feature may be removed later. This commit also adds more instruction fusion cases that need changes in both the decode stage and the funtion units. In this commit, we add some opcode to the function units and fuse the new instruction pairs into these new internal uops. The list of opcodes we add in this commit is shown below: - szewl1: `slli r1, r0, 32` + `srli r1, r0, 31` - szewl2: `slli r1, r0, 32` + `srli r1, r0, 30` - byte2: `srli r1, r0, 8` + `andi r1, r1, 255` - sh4add: `slli r1, r0, 4` + `add r1, r1, r2` - sr30add: `srli r1, r0, 30` + `add r1, r1, r2` - sr31add: `srli r1, r0, 31` + `add r1, r1, r2` - sr32add: `srli r1, r0, 32` + `add r1, r1, r2` - oddadd: `andi r1, r0, 1`` + `add r1, r1, r2` - oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2` - orh48: mask off the first 16 bits and or with another operand (`andi r1, r0, -256`` + `or r1, r1, r2`) Furthermore, this commit adds some complex instruction fusion cases to the decode stage and function units. The complex instruction fusion cases are detected after the instructions are decoded into uop and their CtrlSignals are used for instruction fusion detection. We add the following complex instruction fusion cases: - addwbyte: addw and mask it with 0xff (extract the first byte) - addwbit: addw and mask it with 0x1 (extract the first bit) - logiclsb: logic operation and mask it with 0x1 (extract the first bit) - mulw7: andi 127 and mulw instructions. Input to mul is AND with 0x7f if mulw7 bit is set to true.

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mmu.l2tlb: partially rewrite fsm and miss queue for bug and optimization (#1007) * mmu.l2tlb: l2tlb now support multiple parallel mem accesses 8 missqueue entry and 1 page table worker mq entry only supports page leaf entry ptw supports all the three level entries * mmu.tlb: fix bug of mq.refill_vpn and out.ready * mmu.tlb: fix bug of perf counter * mmu.tlb: l2tlb's l3 now 128 sets and 4 ways * mmu.tlb: miss queue now will 'merge' same mem req addr * mmu.l2tlb: ptw doesn't access last level pte * mmu.l2tlb: add mem req mask into ptw func block_decoupled doesn't work well and has bug in signal ready * mmu.l2tlb: fix bug of sfence to fsm add a new state s_check_pte to ptw fsm now take memPte from outside, doesn't store it inside mem_resp_valid will arrive a cycle before mem_resp_data * mmu.l2tlb: rm some state in fsm * mmu.tlb: set itlb default size * mmu.l2tlb: unkonwn mq wait bug, change code style to avoid it * mmu.l2tlb: opt, mq's entry with cache_l3 would not be blocked * mmu.l2tlb: add many time out assert * mmu.l2tlb: fix bug of mq enq state change & wait_id * Revert "mmu.tlb: l2tlb's l3 now 128 sets and 4 ways" This reverts commit 216e4192e4b01e68ce5502135318bc2473434907. * Revert "mmu.tlb: set itlb default size" This reverts commit 670bf1e408384964c601c0a55defbc767eb80698. * mmu.l2tlb: set miss queue size to 9 and set filter size to 8 if they are equal, itlb may loss its req

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Yinan Xu

commit sha 66c2a07b8b3ab6f7f7d98549d6ec0ccb68220031

backend, rs: parallelize selection and data read (#1018) This commit changes how uop and data are read in reservation stations. It helps the issue timing. Previously, we access payload array and data array after we decide the instructions that we want to issue. This method makes issue selection and array access serialized and brings critial path. In this commit, we add one more read port to payload array and data array. This extra read port is for the oldest instruction. We decide whether to issue the oldest instruction and read uop/data simultaneously. This change reduces the critical path to each selection logic + read + Mux (previously it's selection + arbitration + read). Variable oldestOverride indicates whether we choose the oldest ready instruction instead of the normal selection. An oldestFirst option is added to RSParams to parameterize whether we need the age logic. By default, it is set to true unless the RS is for ALU. If the timing for aged ALU rs meets, we will enable it later.

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Merge branch 'master' of https://github.com/RISCVERS/XiangShan into huancun-merge

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slice: fix arbiter priority issue

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PR closed OpenXiangShan/HuanCun

SinkC: fix bugs
  • add an isProbeAckDataReg signal to control ready and valid signals
  • ReleaseData can not interrupt ProbeAckData(task.ready)
  • ProbeAckData should occupy the write port of bs until it finishes(bs_waddr.valid)
+8 -2

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SinkC: fix bugs

This bug has been fixed in main stream, so close this PR.

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config: use 4MB L3 cache

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slice: eliminate strict mode for tag/dir write

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misc: remove duplicate chisel-tester2

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