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pull request commentllvm/circt

[MSFT] Lower `MSFTModuleOp`s to `HWModuleOp`s

Thanks @mikeurbach !

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[MSFT] Lower `MSFTModuleOp`s to `HWModuleOp`s (#1803)

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[MSFT] Lower `MSFTModuleOp`s to `HWModuleOp`s msft

Part 4 of #1755.

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[MSFT] Lower `MSFTModuleOp`s to `HWModuleOp`s

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[MSFT] Lower `MSFTModuleOp`s to `HWModuleOp`s msft

Part 4 of #1755.

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[MSFT] Add `MSFTModuleOp` (#1801) Adds a moduleop to the MSFT dialect. For now, it's mostly like hw.module but adds parameters to represent the specific parameterization of a parameterized module. Also necessarily adds a msft.output since hw.output expects to be in a hw.module. Step 3 of #1755.

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[MSFT] Add `MSFTModuleOp` msft

Adds a moduleop to the MSFT dialect. For now, it's mostly like hw.module but adds parameters to represent the specific parameterization of a parameterized module. Also necessarily adds a msft.output since hw.output expects to be in a hw.module.

Step 3 of #1755.

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Pull request review commentllvm/circt

[MSFT] Add `MSFTModuleOp`

 def InstanceOp : MSFTOp<"instance", [       `:` functional-type($inputs, results)   }]; }++def OneOrNoBlocksRegion : Region<+  CPred<"::llvm::hasNItemsOrLess($_self, 1)">,+  "region with at most 1 block">;++def MSFTModuleOp : MSFTOp<"module",

You mean on the InstanceOp? Yeah, I think that makes sense, but not strictly related to this PR.

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pull request commentllvm/circt

[MSFT] Add `MSFTModuleOp`

@lattner See #1755 for some of the reasons. Essentially, we need a super set of the attributes (not reflected in this PR) and it would be convenient to have methods on the sugar c++ class to operate on those attributes. The only added attribute in this PR is the parameterization which this module is or was generated. (Each parameterized module will result in one of these per parameterization based on the instantiation parameters.)

It was getting cumbersome to rely on random attributes on hw.module. Also, there may be certain optimizations in the future (e.g. inlining) which we want to prevent or act on specially.

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pull request commentllvm/circt

[MSFT] Add `MSFTModuleOp`

Large portions copied from hw.module and modified where appropriate. Removed the builders and verifiers. Will add them later.

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PR opened llvm/circt

[MSFT] Add `MSFTModuleOp` msft

Adds a moduleop to the MSFT dialect. For now, it's mostly like hw.module but adds parameters to represent the specific parameterization of a parameterized module. Step 3 of #1755.

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Tests

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Andrew Lenharth

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[FIRRTL] Mark don't touch module ports as overdefined (#1796) There was nothing forcing these ports to be overdefined before, so constants could leak through. The undefined flag gets propagated to the instance port moments later. One could remove the don't touch check in visitConnect now, but it's not clear if checking the attributes is cheaper than merging some lattice values.

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Schuyler Eldridge

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[HW] Remove Unneeded getReferencedModule call Fixes #1797. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

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Chris Lattner

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[ExportVerilog] getAllModulePortInfos works on instances now. NFC.

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John Demme

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[HW] [NFC] Finish move of `printModuleSignature` into shared header.

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Merge branch 'main' into msft-moduleop

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Use code in shared header

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[HW] [NFC] Finish move of `printModuleSignature` into shared header.

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Module op printing

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issue commentllvm/circt

[HW] Parameterized Modules, step #2

I think @stephenneuendorffer summed up my Value-based proposal rather eloquently earlier: "why invent another way to define an IR?" (paraphrased).

Following today's discussion, here's -- from what I understood by the end of the meeting -- the crux of why a Value-based proposal isn't ideal:

hw.module @a params: (%width: !hw.param<i8>) ports: () {
  %widthPlusOne = hw.params.add %width, 1
  %widthPlusOneMinusOne hw.params.add %widthPlusOne, -1
  hw.params.definetype "width", %width
  hw.params.definetype "widthPlusOneMinusOne", %widthPlusOneMinusOne
  %c1 = hw.const 1 : !hw.params.typeparam<"width">
  %c2 = hw.const 2 : !hw.params.typeparam<"widthPlusOneMinusOne">
  %three = comb.add %c1, %c2
}

The comb.add verifier needs to ensure that %c1 and %c2 are integers of the same width. The Types of them, however, don't trivially match (pointer-based) so the SSA would have to be evaluated in order to determine the actual type -- which is expensive. (And not possible in the verifier...?)

If we use an attribute-based expression language, however, it is possible to compute the types at/before verification time.... in this case.

There exist, however, cases wherein type equality cannot by resolved locally at all:

hw.module @b params: (width1: #hw.typeparam, width2: #hw.typeparam)
             ports:  (%a: !hw.parameterized_type<width1>, %b: !hw.parameterized_type<width2>) {
  comb.add %a, %b: ?
}

How would the comb.add verifier do type checking here? I don't think it could. The verifier needs contextual information to do the comparison -- which could be different for each instance of the module.

If I'm correct about that, it follows that we'd have to deal with cases wherein verifiers cannot participate in type checking at construction time. Rather, a post-construction instance-hierarchy-traversal (which tracks the contextual parameter values) would be required to verify the types. (This assumes that the parameter values are known to the compiler, which they won't be if one wants to output a parameterized verilog module.) An instance-hierarchy-traversal verification pass is actually worse than the 2 pass IR construction which @stephenneuendorffer was speaking about earlier today, so please someone (@lattner) tell me I'm way off-base and why.

So if we end up in a situation where we just have to accept that the verifiers (in certain cases which could be quite common) cannot check types, why not use my Value based scheme?

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Module parsing

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[Seq] [CompRegOp] Make 'name' non-optional but allow it to be empty (#1772) Make `seq.compreg`'s name follow the same semantics of `sv.reg`.

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John Demme

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[ESI] Make instances match module declarations (#1780) * [ESI] Create one extern module per module parameterization * hw.instance verifier no longer has to ignore extern modules

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Chris Gyurgyik

commit sha 0465fa378066aff1ce2ef756b154117c0d681152

[Calyx] Verify that sources of group ports and assignments are not logically complex. (#1774) As discussed in #1769, some verifiers should be added to avoid giving the sources of group ports / assignments logically complex expressions. Also adds a verifier to ensure that GroupOp isn't being used as a CombGroupOp, and makes the necessary refactoring. This will be removed when native Calyx supports complex arguments for sources.

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Chris Lattner

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[ESI] Switch updateInstance(HWModuleExternOp..) to use convenience builder NFC. This automatically propagates port labels (with a future patch).

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Martin Erhart

commit sha db042fedffe5c66a061b4d4e781c88bfb541e393

[LLHD] Replace remaining standardops with comb ops in tests This should have been part of an earlier commit where we switched from using standard ops for arithmetic operations to comb ops in LLHD

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Chris Gyurgyik

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[Calyx] Add combinational trait. (#1781) This adds a combinational trait to Calyx operations. We can throw this on all non-memory operations for now, since they are all combinational. Eventually we'll need to split this off. Closes #1739. Also fixes a bug where it was considering a memory load as a store, since the address ports are used when both storing and loading to a MemoryOp. A test is added to verify this no longer occurs.

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Prithayan Barua

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[Docs] Fix typo in Doc [NFC] (#1786) Fix typo in Doc

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Prithayan Barua

commit sha 805d7e8be89524f53bf30895469ee78408ea1f6b

[LowerToHW] Add attribute to mark the Design Under Test module [NFC] (#1785) The annotation `sifive.enterprise.firrtl.MarkDUTAnnotation` , marks what is the DUT (and not the testbench). Lower the annotation, to the attribute "DesignUnderTest", during `LowerToHW`. Adds attribute `{DesignUnderTest }` to the module which has this annotation. Other `sv/hw` passes can use this attribute to identify the DUT.

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Chris Lattner

commit sha 64f16a2f5065f6ebd0261c68262f6ca0ddb48ec5

[Calyx] Fix a clang warning identifying a bug. warning: object backing the pointer will be destroyed at the end of the full-expression [-Wdangling-gsl] StringRef portName = valueName(group->getParentOfType<ComponentOp>(), value); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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Chris Lattner

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[tests] Fix tests where the instance/module label names don't line up. This is about to be diagnosed properly.

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Chris Lattner

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[HW] Enhance hw.instance to carry input/result port names. This makes both hw.module* and hw.instance carry an argNames/resultNames array attribute for the port names, and the verifier checks that they line up. This makes various queries on the instances much much faster (because you don't need to resolve the module being referenced) and makes the code more obviously correct in multithreaded situations.

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Chris Lattner

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[ExportVerilog] Remove some now-unnecessary uses of getReferencedModule. NFC.

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Chris Gyurgyik

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[Calyx] [obvious] Update documentation for ComponentOp.

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Prithayan Barua

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[LowerToHW] Update attribute DesignUnderTest to firrtl.DesignUnderTest [NFC] (#1789) Prefix the attribute `DesignUnderTest` with `firrtl` since it defines a `FIRRTL` specific property. Update the docs and tests accordingly. Followup to commit #805d7e8be89524f53bf30895469ee78408ea1f6b

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[obvious] [Calyx] Use SymbolUserOpInterface.

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Chris Gyurgyik

commit sha ddf3b84fbaa78a41309292ac0bdab3ab52d04e2a

[HW] [MSFT] Remove unnecessary assertions in `getReferencedModule` and add SymbolOpUserInterface to MSFT InstanceOp. (#1787) Remove a lot of assertions and checks that are validated by the ODS and `verifyInstanceOp` function. Secondly, use SymbolOpUserInterface in MSFT dialect to avoid O(n) lookup when verifying the InstanceOp.

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[Python] Fixing `InstanceOp` binding and ditching module decorator Fixes the integration tests. Closes #1788.

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John Demme

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Merge branch 'main' into msft-moduleop

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John Demme

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[Seq] Eliminate '_compreg' autogenerate when lowering To address remaining concern in https://github.com/llvm/circt/pull/1772#discussion_r707908878

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[HW] [NFC] Extract out printing/parsing functions for modules (#1773)

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[HW] [NFC] Extract out printing/parsing functions for modules HW

To enable re-use in other dialects.

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issue commentllvm/circt

[HW] Move off of mlir::ModuleOp to hw::DesignOp (or something)

1. It would eliminate the confusing and annoying ModuleOp vs HWModuleOp divide.

To what are you referring? The namespace issue which is the reason for hw::HWModuleOp rather than hw::ModuleOp?

3. It gets CIRCT into a more controlled model, where hw::ModuleOp is tied to hw::DesignOp

I don't see a whole lot of practical value in this. Please elaborate.


It should be pointed out that this change would be quite pervasive -- it would break every line which finds the top level with getParentOfType<ModuleOp>(). Some of this might break silently in cases where you have a builtin.module which contains a hw.design, which I'd image would be necessary to combine non-CIRCT dialects (e.g. for HLS lowering). It could introduce more complexity in non-CIRCT case due to having to reason about multiple symbol tables (the lookup traversal of which has never made sense to me). It would also touch most of the tests. (So if we end up doing this, the integration tests should be run before merging to main.)

While I do agree with the "idealistic cleanup" bit, I still need convincing that this is worth it.

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Pull request review commentllvm/circt

[Seq] [CompRegOp] Make 'name' non-optional but allow it to be empty

 struct CompRegLower : public OpConversionPattern<CompRegOp> {     Location loc = reg.getLoc();      StringAttr name = reg.nameAttr();-    if (!name)+    if (reg.name().empty())

Good point. 4730fe83618c1e19d111800fec9c0e4aa03e4539

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