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silabs-hfegran/cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

https://github.com/silabs-hfegran/cv32e40x

silabs-hfegran

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contributors (According to the first 100)

Silabs-ArjanB
davideschiavone
silabs-oysteink
atraber
bluewww
svenstucki
silabs-halfdan
silabs-oivind
gautschimi
silabs-robin
mp-17
silabs-PaulZ
stmach
MikeOpenHWGroup
michael-platzer
FrancescoConti
strichmo
accuminium
owenchj0
SamuelRiedel
gmarkall
antmas
dawidzim
florent-gwt
jeremybennett
lucabertaccini
Razer6
fabianschuiki
haugoug
GTumbush
silabs-hfegran
jm4rtin
TobiasKaiser
wallento
aignacio
zetalog
OttG
vogelpi
zdogs