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If you are wondering where the data of this site comes from, please visit https://api.github.com/users/sequencer/events. GitMemory does not store any data, but only uses NGINX to cache data for a period of time. The idea behind GitMemory is simply to give users a better reading experience.
Jiuyang Liu sequencer Shanghai, China https://jiuyang.me 0x8D7B5A. I work for open source chip design.

chipsalliance/treadle 95

Chisel/Firrtl execution engine

felixonmars/archriscv-packages 30

Modified Arch Linux packages for archriscv

sequencer/chiselminer-opensource 24

sha256d mining chip written by chisel.

chipsalliance/api-config-chipsalliance 12

A Scala library for Context-Dependent Evironments

cnrv/diplomacy 8

split from rocketchip, try to add test and doc to it.

sequencer/diplomatictester 6

VIP library for you TileLink IP

sequencer/chiselmodel 5

This is a experimental library interacting Chisel based design to foreign language with DPI, to inject arbitrary software model to Chisel and simulate together.

startedrecolic/awesome-hust

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create barnchsequencer/mithril

branch : m1

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fork sequencer/mithril

Pure Rust Monero Miner

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startedRagnaroek/mithril

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push eventsequencer/arithemic

Jiuyang Liu

commit sha cd256c7dbaf8d57aacb618ce85120222bb766e0c

bugfix for modmul.

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push eventsequencer/playground

Jiuyang Liu

commit sha d0cfa2b936e9276ba02c3653f2fabc5c8dcb872c

remove merged PR

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PullRequestReviewEvent

pull request commentchipsalliance/chisel3

Extend BitPat API with relations between BitPats

Since @jackkoenig is on vacation, maybe I can ask reviews from @seldridge or @azidar?

OceanS2000

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pull request commentchipsalliance/chisel3

Signal Trace API

My request is that in src/test/scala, you show what it might look like to generate Verilator config files using this stuff. We could then include that code in chisel3 and/or firrtl as well, but I'd at least like to see what it looks like so we can be sure if tap and view are the right API or not.

And request from @jackkoenig is resolved as well.

sequencer

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PR opened chipsalliance/rocket-chip

bump chisel to 3.5-rc1
+3 -3

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create barnchchipsalliance/rocket-chip

branch : bump_chisel

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startedregymm/SqueakyBoard

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create barnchsequencer/arithemic

branch : modmul

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Jiuyang Liu

commit sha 53963e091aaf2b1aca3d343df3ba206e73a0fe1e

Add test for PrefixGraph.

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pull request commentchipsalliance/chisel3

Just install Z3 from apt-get in CI

cannot image that broke again…

jackkoenig

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issue commentchipsalliance/diplomacy

Re-edit diplomacy documentation.

Assigned to @sinofp Weekly meeting at Diplomacy Doc editing(zoom meeting in Chinese ): Scheduled: Sep 24, 2021 at 20:00 to 21:30, GMT+8

sequencer

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MemberEvent

issue commentchipsalliance/diplomacy

Unit Test

Assigned to @SihaoLiu, Oct. 27 due.

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Scala Steward

commit sha 6aca90241550e57f7752d2bdb572e3c47c40e565

Update sbt-scoverage to 1.9.0

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Jiuyang Liu

commit sha 237a873ee1a85a20a4ab139fdaf7b48ea9bfd32f

Merge pull request #2125 from scala-steward/update/sbt-scoverage-1.9.0 Update sbt-scoverage to 1.9.0

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PR merged chipsalliance/chisel3

Update sbt-scoverage to 1.9.0

Updates org.scoverage:sbt-scoverage from 1.8.2 to 1.9.0. GitHub Release Notes - Version Diff

I'll automatically update this PR to resolve conflicts as long as you don't change it yourself.

If you'd like to skip this version, you can just close this PR. If you have any feedback, just mention me in the comments below.

Configure Scala Steward for your repository with a .scala-steward.conf file.

Have a fantastic day writing Scala!

<details> <summary>Ignore future updates</summary>

Add this to your .scala-steward.conf file to ignore future updates of this dependency:

updates.ignore = [ { groupId = "org.scoverage", artifactId = "sbt-scoverage" } ]

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labels: sbt-plugin-update, semver-minor

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scala-steward

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PullRequestReviewEvent

pull request commentchipsalliance/chisel3

Extend BitPat API with relations between BitPats

LGTM, ask review from @jackkoenig

OceanS2000

comment created time in 12 days

PullRequestReviewEvent

Pull request review commentchipsalliance/chisel3

Extend BitPat API with relations between BitPats

 sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou   }.mkString    override def toString = s"BitPat($rawString)"++  /**+    * If a BitPat overlaps with another BitPat, i.e., exists x : UInt that (x === this) && (x === rhs)+    */+  // overlap iff bitwise: both care (lhs.mask & rhs.mask) => both equal (lhs.value == rhs.value)+  def overlaps(rhs: BitPat): Boolean = ((mask & rhs.mask) & (value ^ rhs.value)) == 0+  /**+    * If a BitPat contains another BitPat+    */+  // contains iff bitwise: lhs care => rhs also care && equal (~(rhs.mask & (value xnor rhs.value)))+  def contains(rhs: BitPat): Boolean = (mask & (~rhs.mask | (value ^ rhs.value))) == 0

maybe contain(not s), I didn't see s in subtract

OceanS2000

comment created time in 12 days

PullRequestReviewEvent

Pull request review commentchipsalliance/chisel3

Extend BitPat API with relations between BitPats

 sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou   }.mkString    override def toString = s"BitPat($rawString)"++  /**+    * If a BitPat overlaps with another BitPat, i.e., exists x : UInt that (x === this) && (x === rhs)+    */+  // overlap iff bitwise: both care (lhs.mask & rhs.mask) => both equal (lhs.value == rhs.value)+  def overlaps(rhs: BitPat): Boolean = ((mask & rhs.mask) & (value ^ rhs.value)) == 0

maybe overlap(not s), I didn't see s in subtract

OceanS2000

comment created time in 12 days

PullRequestReviewEvent
PullRequestReviewEvent

Pull request review commentchipsalliance/chisel3

Extend BitPat API with relations between BitPats

 sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou   }.mkString    override def toString = s"BitPat($rawString)"++  /**+    * If a BitPat overlaps with another BitPat, i.e., exists x : UInt that (x === this) && (x === rhs)+    */+  // overlap iff bitwise: both care (lhs.mask & rhs.mask) => both equal (lhs.value == rhs.value)+  def overlaps(rhs: BitPat): Boolean = ((mask & rhs.mask) & (value ^ rhs.value)) == 0+  /**+    * If a BitPat contains another BitPat+    */+  // contains iff bitwise: lhs care => rhs also care && equal (~(rhs.mask & (value xnor rhs.value)))+  def contains(rhs: BitPat): Boolean = (mask & (~rhs.mask | (value ^ rhs.value))) == 0++  /**+    * Calculate intersection of two BitPats+    * @return A Set of BitPat as the result may not be represented by a single BitPat+    */+  def intersect(rhs: BitPat): Set[BitPat] = {+    if (!overlaps(rhs)) {+      Set()+    } else {+      // intersection => any of them care+      val r_value = this.value | rhs.value+      val r_mask = this.mask | rhs.mask+      // as === is zero extended, the intersection should have be the wider one+      val r_width = this.getWidth max rhs.getWidth+      Set(new BitPat(r_value, r_mask, r_width))+   }+  }++  /**+    * Subtract BitPat rhs from this+    * @return A Set of BitPat as the result may not be represented by a single BitPat+    */+  def subtract(rhs: BitPat): Set[BitPat] = {+    def enumerateBits (mask: BigInt): Seq[BigInt] = {

add @tailrec anno?

OceanS2000

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