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virtualagc/virtualagc 2083

Virtual Apollo Guidance Computer (AGC) software

rburkey2005/cnn-registration 1

A image registration method using convolutional neural network features.

rburkey2005/kicad 1

A mirror of the KiCad development branch, which is hosted at launchpad using bzr (updated every 10 minutes)

rburkey2005/pyul 0

Python port of Yul

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Added code to detect duplicate database entries (by URL)

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The assembly listings for FP6 and FP8 weren't in git, and weren't being tracked.

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"Modern" PTC assembly listing hadn't been updated for some fixed typos in the source code.

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Pull request review commentvirtualagc/virtualagc

Improved scaler logic and counter simulation for yaAGC

 SimulateDV(agc_t *State, uint16_t divisor)     uint16_t l = c(RegL);     int i; -    // Assume A contains the sign of the dividend-    dividend_sign = a & 0100000;+    // Assume A contains the sign of the dividend+    dividend_sign = a & 0100000;++    // Negate A if it was positive+    if (!dividend_sign)+      a = ~a;+    // If A is now -0, take the dividend sign from L+    if (a == 0177777)+      dividend_sign = l & 0100000;+    // Negate L if the dividend is negative.+    if (dividend_sign)+      l = ~l;++    // Add 40000 to L+    l = AddSP16(l, 040000);+    // If this did not cause positive overflow, add one to A+    if (ValueOverflowed(l) != AGC_P1)+      a = AddSP16(a, 1);+    // Initialize the remainder with the current value of A+    remainder = a;++    // Record the sign of the divisor, and then take its absolute value+    divisor_sign = divisor & 0100000;+    if (divisor_sign)+      divisor = ~divisor;+    // Initialize the quotient via a WYD on L (L's sign is placed in bits+    // 16 and 1, and L bits 14-1 are placed in bits 15-2).+    quotient_sign = l & 0100000;+    quotient = quotient_sign | ((l & 037777) << 1) | (quotient_sign >> 15);++    for (i = 0; i < 14; i++)+    {+        // Shift up the quotient+        quotient <<= 1;+        // Perform a WYD on the remainder+        remainder_sign = remainder & 0100000;+        remainder = remainder_sign | ((remainder & 037777) << 1);+        // The sign is only placed in bit 1 if the quotient's new bit 16 is 1+        if ((quotient & 0100000) == 0)+          remainder |= (remainder_sign >> 15);+        // Add the divisor to the remainder+        sum = AddSP16(remainder, divisor);+        if (sum & 0100000)+          {+            // If the resulting sum has its bit 16 set, OR a 1 onto the+            // quotient and take the sum as the new remainder+            quotient |= 1;+            remainder = sum;+          }+    }+    // Restore the proper quotient sign+    a = quotient_sign | (quotient & 077777);++    // The final value for A is negated if the dividend sign and the+    // divisor sign did not match+    c(RegA) = (dividend_sign != divisor_sign) ? ~a : a;+    // The final value for L is negated if the dividend was negative+    c(RegL) = (dividend_sign) ? remainder : ~remainder;+}++//-----------------------------------------------------------------------------+// These functions implement scaler timing logic. The scaler is a 33-stage+// binary counter whose outputs are used to time many things throughout the+// AGC. Each stage has four outputs -- the inverted and noninverted state for+// that stage (named, eg., FS09 and FS09/), and two timing pulses of the form+// FxxA and FxxB. Timing pulse FxxA is emitted when the stage transitions from+// a 1 to a 0, and timing pulse FxxB is emitted when the stage transitions+// from a 0 to a 1. The frequency of each stage can be calculated by the+// forumula (1.024 kHz)/(2^x), where x is the number of the stage.+//+// Our implementation of the scaler omits stages 1 and 2, since they are too+// fast and time things too finely detailed for an emulator to care about.+// We simply advance our scaler counter once at the beginning of every MCT,+// and if that causes stage 3 to increment, we generate all expected+// timing pulses.++// Timepulse F03B generates PIPA data strobes, causing all three to generate+// either a plus or a minus count request. This happens only when FS04 is+// set and FS05 isn't -- i.e, every fourth F03B.+static void+TimingSignalF03B(agc_t * State)+{+    if ((State->ScalerValue & (SCALER_FS05 | SCALER_FS04)) == SCALER_FS04)+      PulseOutput(State, OUTPUT_PIPA_DATA);+}++// Timepulse F04A clears the uplink-too-fast bit, which is set by each+// incoming uplink bit. If another uplink bit arrives before F04A occurs,+// the new bit will be dropped and the computer will be notified via+// channel 33 bit 11.+static void+TimingSignalF04A(agc_t * State)+{+    State->UplinkTooFast = 0;+}++// Timepulse F05A is far and away the busiest timing signal. It is used +// for some standby-powered circuitry that monitors voltage levels. We +// are not simulating power supply failures, and the input voltage must+// go well below its lower limit for the AGC power supply outputs to+// dip, so we only monitor the input voltage.+// +// It checks inputs for the three input traps (31A, 31B, and 32) and+// sets a bit for each if they are active. If F05B occurs before a+// triggered trap gets reset, a HANDRUPT will be generated.+//+// This timepulse also generates many output count requests: the BMAG/RHC+// and RNRAD input counters, and all output counters use this timepulse.+static int+TimingSignalF05A(agc_t * State)+{+    int CausedRestart = 0;+    int i = 0;+    int PulseType = 0;++    // First, perform standby-powered stuff. Has our input voltage+    // remained below the limit since F05B?+    if (State->InputVoltageLow)+    {+        // The input voltage is bad. If we're in standby, this generates+        // an input to the warning filter.+        if (State->Standby)+            State->GeneratedWarning = 1;++        if (!InhibitAlarms)+        {+            // If the alarm isn't disabled, the computer will be held in+            // restart (via signal STRT1) until the next F05A in which the+            // the voltage is back within limits. Trigger a GOJAM and set+            // the appropriate CH77 bit.+            State->RestartHold = 1;+            State->InputChannel[077] |= CH77_VOLTAGE_FAIL;+            CausedRestart = 1;+        }+    }+    else+    {+        // Voltage is good, so de-assert the STRT1 restart hold+        State->RestartHold = 0;+    }++    // That's it for standby-powered stuff, so leave if we're in standby+    if (State->Standby)+        return CausedRestart;++    // Set the PIPA pulse missing monitoring bits for each PIPA+    State->PipaMissX = 1;+    State->PipaMissY = 1;+    State->PipaMissZ = 1;++    // Check for any of the input traps to be triggered. If they are, and+    // the cause of the triggering doesn't go away before F05B, we'll+    // generate a HANDRUPT.+    if (State->Trap31A && ((State->InputChannel[031] & 000077) != 000077))+        State->Trap31APending = 1;++    if (State->Trap31B && ((State->InputChannel[031] & 007700) != 007700))+        State->Trap31BPending = 1;++    if (State->Trap32 && ((State->InputChannel[032] & 001777) != 001777))+        State->Trap32Pending = 1;++    // Check for RHC input pulses+    for (i = 0; i < 3; i++)+    {+        if (State->RHCCounts[i] > 0)+        {+            State->RHCCounts[i]--;+            if (State->InputChannel[013] & 0200)+                CounterRequest(State, COUNTER_RHCP + i, COUNTER_CELL_PLUS);+        }+        else if (State->RHCCounts[i] < 0)+        {+            State->RHCCounts[i]++;+            if (State->InputChannel[013] & 0200)+                CounterRequest(State, COUNTER_RHCP + i, COUNTER_CELL_MINUS);+        }+    }++    // Generate radar count requests if a valid radar is selected+    if (State->RadarSync)+    {+        if (State->InputChannel[013] & 04)+            PulseOutput(State, OUTPUT_LR_SYNC);+        else if ((State->InputChannel[013] & 03) != 0)+            PulseOutput(State, OUTPUT_RR_SYNC);+    }++    // Generate gyro drive pulses+    if (State->InputChannel[014] & 01000)+    {+        // At least one DINC is always generated regardless of the value+        // in the GYROCMD counter. The result of that DINC will determine+        // what happens next; if it generates a ZOUT, the drive active bit+        // and channel 14 bit 10 are cleared. Otherwise, the active bit is+        // set, which allows these F05A timing signals to generate drive+        // pulses to the gyros.+        CounterRequest(State, COUNTER_GYROCMD, COUNTER_CELL_PLUS);+        if (State->GyroDriveActive)+          PulseOutput(State, OUTPUT_GYROCMD_SET);+    }+    else+        State->GyroDriveActive = 0;++    // Generate CDU drive pulses if their respective channel 14 bits are+    // set. The output pulses themselves are generated during the DINC,+    // with a ZOUT resetting the channel 14 bit to disable the counter.+    if (State->InputChannel[014] & 040000)+      CounterRequest(State, COUNTER_CDUXCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 020000)+      CounterRequest(State, COUNTER_CDUYCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 010000)+      CounterRequest(State, COUNTER_CDUZCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 04000)+      CounterRequest(State, COUNTER_OPTYCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 02000)+      CounterRequest(State, COUNTER_OPTXCMD, COUNTER_CELL_PLUS);++    // THRUST and EMSD operate identically, with THRUST being enabled by+    // channel 14 bit 4, and EMSD being enabled by bit 5. For these,+    // F05A is responsible for both generating DINC requests *and*+    // sending the resulting output pulses. A POUT or a MOUT on the+    // first DINC will set a bit that allows plus or minus pulses,+    // respectively, on subsequent F05As. These bits are never cleared+    // until the CH14 enable bits are cleared, so if the value in the+    // counter changes sign for some reason, both plus and minus output+    // pulses will be generated until the counter is disabled.+    if (State->InputChannel[014] & 010)+    {+        if (State->ThrustPlusActive)+          PulseOutput(State, OUTPUT_THRUST_PLUS);+        if (State->ThrustMinusActive)+          PulseOutput(State, OUTPUT_THRUST_MINUS);++        CounterRequest(State, COUNTER_THRUST, COUNTER_CELL_PLUS);+    }++    if (State->InputChannel[014] & 020)+    {+        if (State->EMSPlusActive)+          PulseOutput(State, OUTPUT_EMSD_PLUS);+        if (State->EMSMinusActive)+          PulseOutput(State, OUTPUT_EMSD_MINUS);++        CounterRequest(State, COUNTER_EMSD, COUNTER_CELL_PLUS);+    }++    // OUTLINK and ALTM are also almost identical. OUTLINK is enabled+    // by channel 14 bit 1. After this bit is set to 1, nothing happens+    // until the following GTSET, which sets up the output circuitry.+    // The first F05A after this GTSET, a "1" output pulse is generated+    // as a sync marker. This F05A will also generate a SHINC request,+    // as will every subsequent F05A until the outlink counter is+    // disabled by another GTSET. +    //+    // The first F05A of an outlink will also clear the enable flip-flop,+    // channel 14 bit 1. However, this bit will still read as 1 to+    // software, because for reading its state is ORed together with+    // the "outlink active" flip-flop.+    //+    // ALTM behaves almost identically. It is enabled by channel 14 bit+    // 3. It can target one of two pairs of output pins; altitude if+    // channel 14 bit 2 is 0, and altitude rate if it is 1. This+    // selection is "checked" with every output pulse, so misbehaving+    // software can change which interface is being addressed in the+    // middle of an output cycle.+    if (State->OutlinkActive)+    {+        if (State->OutlinkStarting)+        {+            State->OutlinkStarting = 0;+            PulseOutput(State, OUTPUT_OUTLINK_ONE);+            State->InputChannel[014] &= ~01;+        }+        else+          CounterRequest(State, COUNTER_OUTLINK, COUNTER_CELL_ZERO);+    }++    if (State->AltActive)+    {+        if (State->AltStarting)+        {+            State->AltStarting = 0;+            State->InputChannel[014] &= ~04;+            if (State->InputChannel[014] & 02)+              PulseOutput(State, OUTPUT_ALTRATE_ONE);+            else+              PulseOutput(State, OUTPUT_ALT_ONE);+        }+        else+          CounterRequest(State, COUNTER_ALTM, COUNTER_CELL_ZERO);+    }++    return CausedRestart;+}++// Timepulse F05B checks to see if any voltage sources are out of limits,+// and if they are, notes it down. If the problem hasn't been resolved+// by F05A, we'll generate an alarm. It also generates HANDRUPTs if any+// of the input traps are enabled and triggered.+// Timing pulses GTSET, GTRST, and GTONE are potentially generated,+// depending on the state of scaler stages 6-9. These pulses are used+// by the radar, outlink, and altimeter interfaces.+static void+TimingSignalF05B(agc_t * State)+{+    unsigned GtsetType;+    // If the input voltage is below the voltage fail circuit threshold,+    // set a bit for F05A to check.+    if (State->InputVoltagemV < VFAIL_THRESHOLD)+        State->InputVoltageLow = 1;++    if (State->Standby)+        return;++    // Set the PIPA fail bit if any expected PIPA pulses were not received+    if (State->PipaMissX || State->PipaMissY || State->PipaMissZ)+      State->InputChannel[033] &= ~010000;++    // If any of the input traps are pending, generate a HANDRUPT and+    // disable the tripped trap.+    if (State->Trap31APending)+    {+        State->Trap31A = 0;+        State->Trap31APending = 0;+        State->InterruptRequests[RUPT_HANDRUPT] = 1;+    }++    if (State->Trap31BPending)+    {+        State->Trap31B = 0;+        State->Trap31BPending = 0;+        State->InterruptRequests[RUPT_HANDRUPT] = 1;+    }++    if (State->Trap32Pending)+    {+        State->Trap32 = 0;+        State->Trap32Pending = 0;+        State->InterruptRequests[RUPT_HANDRUPT] = 1;+    }++    // Handled GTSET, GTRST, and GTON-driven logic+    GtsetType = State->ScalerValue & SCALER_GTSET;+    if (GtsetType == SCALER_GTSET)+    {+        // If the radar gate counter has reached 9, begin generating sync+        // pulses and getting count requests back.+        if (State->RadarGateCounter == 9)+          State->RadarSync = 1;++        // Outlink and tape meter outputs function identically; GTSET will+        // begin an outgoing pulse sequence if there is not one already+        // active, otherwise it will end the ongoing one and clear the+        // channel enable bit.+        if (State->OutlinkActive)+        {+            State->InputChannel[014] &= ~01;+            State->OutlinkActive = 0;+        }+        else if (State->InputChannel[014] & 01)+        {+            State->OutlinkActive = 1;+            State->OutlinkStarting = 1;+        }++        if (State->AltActive)+        {+            State->InputChannel[014] &= ~04;+            State->AltActive = 0;+        }+        else if (State->InputChannel[014] & 04)+        {+            State->AltActive = 1;+            State->AltStarting = 1;+        }+    }+    else if (GtsetType == SCALER_GTRST)+    {+        // If a radar sync was active, stop it, generate a RADARUPT, and+        // reset all of the related state information+        if (State->RadarSync)+        {+            State->InterruptRequests[RUPT_RADARUPT] = 1;+            State->InputChannel[013] &= ~010;

Oh, I wasn't making any hints about reducing clutter. The Virtual AGC Project probably seems to many people to be 100% clutter anyway! :smile: I just wanted to make sure you weren't having expectations accidentally doomed to failure. Which you're not.

thewonderidiot

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Added note to change log about reprocessing a couple of older docs. More progress on document library database and autogeneration.

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Pull request review commentvirtualagc/virtualagc

Improved scaler logic and counter simulation for yaAGC

 SimulateDV(agc_t *State, uint16_t divisor)     uint16_t l = c(RegL);     int i; -    // Assume A contains the sign of the dividend-    dividend_sign = a & 0100000;+    // Assume A contains the sign of the dividend+    dividend_sign = a & 0100000;++    // Negate A if it was positive+    if (!dividend_sign)+      a = ~a;+    // If A is now -0, take the dividend sign from L+    if (a == 0177777)+      dividend_sign = l & 0100000;+    // Negate L if the dividend is negative.+    if (dividend_sign)+      l = ~l;++    // Add 40000 to L+    l = AddSP16(l, 040000);+    // If this did not cause positive overflow, add one to A+    if (ValueOverflowed(l) != AGC_P1)+      a = AddSP16(a, 1);+    // Initialize the remainder with the current value of A+    remainder = a;++    // Record the sign of the divisor, and then take its absolute value+    divisor_sign = divisor & 0100000;+    if (divisor_sign)+      divisor = ~divisor;+    // Initialize the quotient via a WYD on L (L's sign is placed in bits+    // 16 and 1, and L bits 14-1 are placed in bits 15-2).+    quotient_sign = l & 0100000;+    quotient = quotient_sign | ((l & 037777) << 1) | (quotient_sign >> 15);++    for (i = 0; i < 14; i++)+    {+        // Shift up the quotient+        quotient <<= 1;+        // Perform a WYD on the remainder+        remainder_sign = remainder & 0100000;+        remainder = remainder_sign | ((remainder & 037777) << 1);+        // The sign is only placed in bit 1 if the quotient's new bit 16 is 1+        if ((quotient & 0100000) == 0)+          remainder |= (remainder_sign >> 15);+        // Add the divisor to the remainder+        sum = AddSP16(remainder, divisor);+        if (sum & 0100000)+          {+            // If the resulting sum has its bit 16 set, OR a 1 onto the+            // quotient and take the sum as the new remainder+            quotient |= 1;+            remainder = sum;+          }+    }+    // Restore the proper quotient sign+    a = quotient_sign | (quotient & 077777);++    // The final value for A is negated if the dividend sign and the+    // divisor sign did not match+    c(RegA) = (dividend_sign != divisor_sign) ? ~a : a;+    // The final value for L is negated if the dividend was negative+    c(RegL) = (dividend_sign) ? remainder : ~remainder;+}++//-----------------------------------------------------------------------------+// These functions implement scaler timing logic. The scaler is a 33-stage+// binary counter whose outputs are used to time many things throughout the+// AGC. Each stage has four outputs -- the inverted and noninverted state for+// that stage (named, eg., FS09 and FS09/), and two timing pulses of the form+// FxxA and FxxB. Timing pulse FxxA is emitted when the stage transitions from+// a 1 to a 0, and timing pulse FxxB is emitted when the stage transitions+// from a 0 to a 1. The frequency of each stage can be calculated by the+// forumula (1.024 kHz)/(2^x), where x is the number of the stage.+//+// Our implementation of the scaler omits stages 1 and 2, since they are too+// fast and time things too finely detailed for an emulator to care about.+// We simply advance our scaler counter once at the beginning of every MCT,+// and if that causes stage 3 to increment, we generate all expected+// timing pulses.++// Timepulse F03B generates PIPA data strobes, causing all three to generate+// either a plus or a minus count request. This happens only when FS04 is+// set and FS05 isn't -- i.e, every fourth F03B.+static void+TimingSignalF03B(agc_t * State)+{+    if ((State->ScalerValue & (SCALER_FS05 | SCALER_FS04)) == SCALER_FS04)+      PulseOutput(State, OUTPUT_PIPA_DATA);+}++// Timepulse F04A clears the uplink-too-fast bit, which is set by each+// incoming uplink bit. If another uplink bit arrives before F04A occurs,+// the new bit will be dropped and the computer will be notified via+// channel 33 bit 11.+static void+TimingSignalF04A(agc_t * State)+{+    State->UplinkTooFast = 0;+}++// Timepulse F05A is far and away the busiest timing signal. It is used +// for some standby-powered circuitry that monitors voltage levels. We +// are not simulating power supply failures, and the input voltage must+// go well below its lower limit for the AGC power supply outputs to+// dip, so we only monitor the input voltage.+// +// It checks inputs for the three input traps (31A, 31B, and 32) and+// sets a bit for each if they are active. If F05B occurs before a+// triggered trap gets reset, a HANDRUPT will be generated.+//+// This timepulse also generates many output count requests: the BMAG/RHC+// and RNRAD input counters, and all output counters use this timepulse.+static int+TimingSignalF05A(agc_t * State)+{+    int CausedRestart = 0;+    int i = 0;+    int PulseType = 0;++    // First, perform standby-powered stuff. Has our input voltage+    // remained below the limit since F05B?+    if (State->InputVoltageLow)+    {+        // The input voltage is bad. If we're in standby, this generates+        // an input to the warning filter.+        if (State->Standby)+            State->GeneratedWarning = 1;++        if (!InhibitAlarms)+        {+            // If the alarm isn't disabled, the computer will be held in+            // restart (via signal STRT1) until the next F05A in which the+            // the voltage is back within limits. Trigger a GOJAM and set+            // the appropriate CH77 bit.+            State->RestartHold = 1;+            State->InputChannel[077] |= CH77_VOLTAGE_FAIL;+            CausedRestart = 1;+        }+    }+    else+    {+        // Voltage is good, so de-assert the STRT1 restart hold+        State->RestartHold = 0;+    }++    // That's it for standby-powered stuff, so leave if we're in standby+    if (State->Standby)+        return CausedRestart;++    // Set the PIPA pulse missing monitoring bits for each PIPA+    State->PipaMissX = 1;+    State->PipaMissY = 1;+    State->PipaMissZ = 1;++    // Check for any of the input traps to be triggered. If they are, and+    // the cause of the triggering doesn't go away before F05B, we'll+    // generate a HANDRUPT.+    if (State->Trap31A && ((State->InputChannel[031] & 000077) != 000077))+        State->Trap31APending = 1;++    if (State->Trap31B && ((State->InputChannel[031] & 007700) != 007700))+        State->Trap31BPending = 1;++    if (State->Trap32 && ((State->InputChannel[032] & 001777) != 001777))+        State->Trap32Pending = 1;++    // Check for RHC input pulses+    for (i = 0; i < 3; i++)+    {+        if (State->RHCCounts[i] > 0)+        {+            State->RHCCounts[i]--;+            if (State->InputChannel[013] & 0200)+                CounterRequest(State, COUNTER_RHCP + i, COUNTER_CELL_PLUS);+        }+        else if (State->RHCCounts[i] < 0)+        {+            State->RHCCounts[i]++;+            if (State->InputChannel[013] & 0200)+                CounterRequest(State, COUNTER_RHCP + i, COUNTER_CELL_MINUS);+        }+    }++    // Generate radar count requests if a valid radar is selected+    if (State->RadarSync)+    {+        if (State->InputChannel[013] & 04)+            PulseOutput(State, OUTPUT_LR_SYNC);+        else if ((State->InputChannel[013] & 03) != 0)+            PulseOutput(State, OUTPUT_RR_SYNC);+    }++    // Generate gyro drive pulses+    if (State->InputChannel[014] & 01000)+    {+        // At least one DINC is always generated regardless of the value+        // in the GYROCMD counter. The result of that DINC will determine+        // what happens next; if it generates a ZOUT, the drive active bit+        // and channel 14 bit 10 are cleared. Otherwise, the active bit is+        // set, which allows these F05A timing signals to generate drive+        // pulses to the gyros.+        CounterRequest(State, COUNTER_GYROCMD, COUNTER_CELL_PLUS);+        if (State->GyroDriveActive)+          PulseOutput(State, OUTPUT_GYROCMD_SET);+    }+    else+        State->GyroDriveActive = 0;++    // Generate CDU drive pulses if their respective channel 14 bits are+    // set. The output pulses themselves are generated during the DINC,+    // with a ZOUT resetting the channel 14 bit to disable the counter.+    if (State->InputChannel[014] & 040000)+      CounterRequest(State, COUNTER_CDUXCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 020000)+      CounterRequest(State, COUNTER_CDUYCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 010000)+      CounterRequest(State, COUNTER_CDUZCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 04000)+      CounterRequest(State, COUNTER_OPTYCMD, COUNTER_CELL_PLUS);+    if (State->InputChannel[014] & 02000)+      CounterRequest(State, COUNTER_OPTXCMD, COUNTER_CELL_PLUS);++    // THRUST and EMSD operate identically, with THRUST being enabled by+    // channel 14 bit 4, and EMSD being enabled by bit 5. For these,+    // F05A is responsible for both generating DINC requests *and*+    // sending the resulting output pulses. A POUT or a MOUT on the+    // first DINC will set a bit that allows plus or minus pulses,+    // respectively, on subsequent F05As. These bits are never cleared+    // until the CH14 enable bits are cleared, so if the value in the+    // counter changes sign for some reason, both plus and minus output+    // pulses will be generated until the counter is disabled.+    if (State->InputChannel[014] & 010)+    {+        if (State->ThrustPlusActive)+          PulseOutput(State, OUTPUT_THRUST_PLUS);+        if (State->ThrustMinusActive)+          PulseOutput(State, OUTPUT_THRUST_MINUS);++        CounterRequest(State, COUNTER_THRUST, COUNTER_CELL_PLUS);+    }++    if (State->InputChannel[014] & 020)+    {+        if (State->EMSPlusActive)+          PulseOutput(State, OUTPUT_EMSD_PLUS);+        if (State->EMSMinusActive)+          PulseOutput(State, OUTPUT_EMSD_MINUS);++        CounterRequest(State, COUNTER_EMSD, COUNTER_CELL_PLUS);+    }++    // OUTLINK and ALTM are also almost identical. OUTLINK is enabled+    // by channel 14 bit 1. After this bit is set to 1, nothing happens+    // until the following GTSET, which sets up the output circuitry.+    // The first F05A after this GTSET, a "1" output pulse is generated+    // as a sync marker. This F05A will also generate a SHINC request,+    // as will every subsequent F05A until the outlink counter is+    // disabled by another GTSET. +    //+    // The first F05A of an outlink will also clear the enable flip-flop,+    // channel 14 bit 1. However, this bit will still read as 1 to+    // software, because for reading its state is ORed together with+    // the "outlink active" flip-flop.+    //+    // ALTM behaves almost identically. It is enabled by channel 14 bit+    // 3. It can target one of two pairs of output pins; altitude if+    // channel 14 bit 2 is 0, and altitude rate if it is 1. This+    // selection is "checked" with every output pulse, so misbehaving+    // software can change which interface is being addressed in the+    // middle of an output cycle.+    if (State->OutlinkActive)+    {+        if (State->OutlinkStarting)+        {+            State->OutlinkStarting = 0;+            PulseOutput(State, OUTPUT_OUTLINK_ONE);+            State->InputChannel[014] &= ~01;+        }+        else+          CounterRequest(State, COUNTER_OUTLINK, COUNTER_CELL_ZERO);+    }++    if (State->AltActive)+    {+        if (State->AltStarting)+        {+            State->AltStarting = 0;+            State->InputChannel[014] &= ~04;+            if (State->InputChannel[014] & 02)+              PulseOutput(State, OUTPUT_ALTRATE_ONE);+            else+              PulseOutput(State, OUTPUT_ALT_ONE);+        }+        else+          CounterRequest(State, COUNTER_ALTM, COUNTER_CELL_ZERO);+    }++    return CausedRestart;+}++// Timepulse F05B checks to see if any voltage sources are out of limits,+// and if they are, notes it down. If the problem hasn't been resolved+// by F05A, we'll generate an alarm. It also generates HANDRUPTs if any+// of the input traps are enabled and triggered.+// Timing pulses GTSET, GTRST, and GTONE are potentially generated,+// depending on the state of scaler stages 6-9. These pulses are used+// by the radar, outlink, and altimeter interfaces.+static void+TimingSignalF05B(agc_t * State)+{+    unsigned GtsetType;+    // If the input voltage is below the voltage fail circuit threshold,+    // set a bit for F05A to check.+    if (State->InputVoltagemV < VFAIL_THRESHOLD)+        State->InputVoltageLow = 1;++    if (State->Standby)+        return;++    // Set the PIPA fail bit if any expected PIPA pulses were not received+    if (State->PipaMissX || State->PipaMissY || State->PipaMissZ)+      State->InputChannel[033] &= ~010000;++    // If any of the input traps are pending, generate a HANDRUPT and+    // disable the tripped trap.+    if (State->Trap31APending)+    {+        State->Trap31A = 0;+        State->Trap31APending = 0;+        State->InterruptRequests[RUPT_HANDRUPT] = 1;+    }++    if (State->Trap31BPending)+    {+        State->Trap31B = 0;+        State->Trap31BPending = 0;+        State->InterruptRequests[RUPT_HANDRUPT] = 1;+    }++    if (State->Trap32Pending)+    {+        State->Trap32 = 0;+        State->Trap32Pending = 0;+        State->InterruptRequests[RUPT_HANDRUPT] = 1;+    }++    // Handled GTSET, GTRST, and GTON-driven logic+    GtsetType = State->ScalerValue & SCALER_GTSET;+    if (GtsetType == SCALER_GTSET)+    {+        // If the radar gate counter has reached 9, begin generating sync+        // pulses and getting count requests back.+        if (State->RadarGateCounter == 9)+          State->RadarSync = 1;++        // Outlink and tape meter outputs function identically; GTSET will+        // begin an outgoing pulse sequence if there is not one already+        // active, otherwise it will end the ongoing one and clear the+        // channel enable bit.+        if (State->OutlinkActive)+        {+            State->InputChannel[014] &= ~01;+            State->OutlinkActive = 0;+        }+        else if (State->InputChannel[014] & 01)+        {+            State->OutlinkActive = 1;+            State->OutlinkStarting = 1;+        }++        if (State->AltActive)+        {+            State->InputChannel[014] &= ~04;+            State->AltActive = 0;+        }+        else if (State->InputChannel[014] & 04)+        {+            State->AltActive = 1;+            State->AltStarting = 1;+        }+    }+    else if (GtsetType == SCALER_GTRST)+    {+        // If a radar sync was active, stop it, generate a RADARUPT, and+        // reset all of the related state information+        if (State->RadarSync)+        {+            State->InterruptRequests[RUPT_RADARUPT] = 1;+            State->InputChannel[013] &= ~010;

@michaelfranzl Are you by chance making these suggestions in the expectation they'll make their way into the main branch of the yaAGC code? I ask, because your patches are being made against a code branch that it seems clear (from the creator) is not going to be merged soon, if ever, into main. In the meantime, your patch suggestions are being viewed as something having to do exclusively with this side-branch of the code, and are essentially being ignored as candidates for the inclusion in the main branch of themselves.

thewonderidiot

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