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OSCPU/NutShell 887

RISC-V SoC designed by students in UCAS

shinezyy/gem5_data_proc 1

data preprocessing scripts for gem5 output

poemonsense/MultiKeySort 0

Multi-keyword Sort Project for Data Structure in UCAS

poemonsense/nus-cs3211 0

Projects for CS3211 Parallel and Concurrent Programming, National University of Singapore, AY 2017-18

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RISC-V Instruction Set Manual

poemonsense/riscv-linux 0

RISC-V Linux Port

sailordiary/ship-identification 0

Ship Identification with General Object Detection Frameworks (BDCI 2017)

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SpencerL-Y/SparseMatLib 0

A Sparse Matrix Library. Final project of data structure course of UCAS.

yzs15/mahjong 0

面向对象的程序设计大作业

pull request commentOpenXiangShan/XiangShan

mem: update block load logic

[Generated by IPC robot] commit: a2cb1e58f77dfad2f1011387746f34a702c0b060

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
a2cb1e5 2.293 1.032 1.528 1.096 1.397 0.266 1.717 1.661 2.213 2.279 0.628

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
c33a770 2.265 1.039 1.527 1.095 1.420 0.266 1.644 1.586 2.205 2.250 0.616
b6c0697 2.274 1.043 1.534 1.096 1.420 0.266 1.646 1.606 2.208 2.252 0.612
bf08468 2.259 1.041 1.536 1.096 1.425 0.266 1.649 1.611 2.202 2.272 0.613
ecf1a4b 2.261 1.043 1.537 1.096 1.419 0.266 1.658 1.632 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
AugustusWillisWang

comment created time in 11 minutes

issue commentOpenXiangShan/XiangShan

请教roq中的intrEnable信号

这一块涉及到特权级的部分,因为不涉及到性能,但能够保证功能正确。我们的处理比较粗暴,上一次没有足够时间来进行细调,欢迎给我们提供优化思路

daxxyy123

comment created time in 2 hours

issue commentOpenXiangShan/XiangShan

请教roq中的intrEnable信号

  1. 我们现在CSR会在执行的时候就写入,发出中断,会导致中断触发,但这条指令实际已经执行却被标记了异常

  2. MMIO和CSR有类似的,会在指令实际提交之前,就完成MMIO的读写,如果发生中断,同样会导致这条指令实际已经执行却被标记了异常

daxxyy123

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commit sha aa2e1f32ff0c5d5162f33321aba64467fcef5cac

regfile: manually reset every registers This commit adds manual reset for every register in Regfile. Previously the reset is done by add reset values to the registers. However, physically general-purpose register file does not have reset values. Since all the regfile always has the same writeback data, we don't need to explicitly assign reset data.

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pull request commentOpenXiangShan/XiangShan

Modify FTB replacement strategy to PLRU

[Generated by IPC robot] commit: b83169c7f8e90c80417ac9271c4c12b98af5d306

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
b83169c 2.281 1.047 1.536 1.096 1.440 0.265 1.627 1.625 2.203 2.249 0.616

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
c33a770 2.265 1.039 1.420 0.266 1.644 2.250 0.616
b6c0697 2.274 1.043 1.534 1.096 1.420 0.266 1.646 1.606 2.208 2.252 0.612
bf08468 2.259 1.041 1.536 1.096 1.425 0.266 1.649 1.611 2.202 2.272 0.613
ecf1a4b 2.261 1.043 1.537 1.096 1.419 0.266 1.658 1.632 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
zoujr

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pull request commentOpenXiangShan/XiangShan

MissQueue: fix perf bug when MissQ merges load miss

[Generated by IPC robot] commit: f2b9333d71bb82c1bd990b5de8b5832f146ba576

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
f2b9333 2.256 1.042 1.528 1.095 1.420 0.266 1.625 1.612 2.211 2.266 0.615

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
b6c0697 2.274 1.420 0.266 1.646 2.252 0.612
bf08468 2.259 1.041 1.536 1.096 1.425 0.266 1.649 1.611 2.202 2.272 0.613
ecf1a4b 2.261 1.043 1.537 1.096 1.419 0.266 1.658 1.632 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
linjuanZ

comment created time in 15 hours

PR opened OpenXiangShan/XiangShan

regfile: manually reset every registers

This commit adds manual reset for every register in Regfile. Previously the reset is done by add reset values to the registers. However, physically general-purpose register file does not have reset values.

Since all the regfile always has the same writeback data, we don't need to explicitly assign reset data.

+87 -741

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branch : fix-regfile-reset

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pull request commentOpenXiangShan/XiangShan

MissQueue: fix perf bug when MissQ merges load miss

[Generated by IPC robot] commit: f0c6502660290ba9869b64da22cbe30d46fc695a

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
f0c6502 2.267 1.041 1.537 1.096 1.420 0.265 1.608 1.599 2.209 2.244 0.614

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
bf08468 2.259 1.041 1.536 1.096 1.425 0.266 1.649 1.611 2.202 2.272 0.613
ecf1a4b 2.261 1.043 1.537 1.096 1.419 0.266 1.658 1.632 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
linjuanZ

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pull request commentOpenXiangShan/XiangShan

MissQueue: fix perf bug when MissQ merges load miss

[Generated by IPC robot] commit: f0c6502660290ba9869b64da22cbe30d46fc695a

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
f0c6502 2.267 1.041 1.537 1.096 1.420 0.265 1.608 1.599 2.209 2.244 0.614

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
bf08468 2.259 1.041 1.536 1.096 1.425 0.266 1.649 1.611 2.202 2.272 0.613
ecf1a4b 2.261 1.043 1.537 1.096 1.419 0.266 1.658 1.632 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
linjuanZ

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pull request commentOpenXiangShan/XiangShan

FTQ: Fix the false hit bug when run mcf

[Generated by IPC robot] commit: 65fddcf0358a85e75e3881fcfda6be033c239922

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
65fddcf 2.227 1.035 1.539 1.095 1.420 0.266 1.657 1.615 2.201 2.255 0.617

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
bf08468 2.259 1.041 1.536 1.096 1.425 0.266 1.649 1.611 2.202 2.272 0.613
ecf1a4b 2.261 1.043 1.537 1.096 1.419 0.266 1.658 1.632 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
zoujr

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pull request commentOpenXiangShan/XiangShan

mem: update block load logic

[Generated by IPC robot] commit: 8057bb3f6f073f302778283f533a50159b549b8f

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
8057bb3 2.308 1.036 1.528 1.096 1.399 0.265 1.700 1.655 2.214 2.264 0.628

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
bf08468 2.259 1.041 1.425 0.266 1.649 2.272 0.613
ecf1a4b 2.261 1.043 1.419 0.266 1.658 2.208 2.258 0.615
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
AugustusWillisWang

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pull request commentOpenXiangShan/XiangShan

FTQ: Fix the false hit bug when run mcf

[Generated by IPC robot] commit: 3ad99c7ff9c928dc40cc7d4b0ec7ca0c83ec26eb

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
3ad99c7 2.256 1.045 1.534 1.097 1.421 0.265 1.631 1.626 2.211 2.239 0.614

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
bf08468 2.259 1.649
ecf1a4b 2.261 1.658
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
zoujr

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pull request commentOpenXiangShan/XiangShan

mmu.l2tlb: set l2tlb's l2 to 32 sets and 2 ways

[Generated by IPC robot] commit: d73b93e94f92143f0b0b35130b8ef73d56ac4ada

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
d73b93e 2.280 1.039 1.542 1.096 1.423 0.266 1.647 1.629 2.204 2.259 0.615

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
c9ebdf9 2.270 1.030 1.530 1.094 1.416 0.264 1.641 1.612 2.200 2.021 0.614
a1ea7f7 2.259 1.029 1.529 1.095 1.417 0.264 1.641 1.625 2.199 2.025 0.613
Lemover

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pull request commentOpenXiangShan/XiangShan

mmu.tlb: ptw resp will refill both ld & st tlb

[Generated by IPC robot] commit: c7f95ebdfeeb5da8317b6d624dddd81bf63a0e63

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
c7f95eb 2.262 1.043 1.535 1.096 1.423 0.266 1.649 1.614 2.207 2.249 0.612

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
82d348f 2.276 1.045 1.537 1.096 1.421 0.266 1.625 1.623 2.203 2.269 0.616
ef90f6b 2.258 1.044 1.538 1.096 1.423 0.266 1.613 1.636 2.205 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
c9ebdf9 2.270 1.030 1.530 1.094 1.416 0.264 1.641 1.612 2.200 2.021 0.614
a1ea7f7 2.259 1.029 1.529 1.095 1.417 0.264 1.641 1.625 2.199 2.025 0.613
Lemover

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pull request commentOpenXiangShan/XiangShan

memBlock.atomic: when addr_valid, just access tlb, ignore data_valid

[Generated by IPC robot] commit: 5e4d29bac758cdaaef8f6e6a71ed846f295fef5d

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
5e4d29b 2.246 1.035 1.536 1.098 1.421 0.265 1.627 1.632 2.208 2.247 0.615

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
ef90f6b 2.258 1.423 0.266 1.613 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
c9ebdf9 2.270 1.030 1.530 1.094 1.416 0.264 1.641 1.612 2.200 2.021 0.614
a1ea7f7 2.259 1.029 1.529 1.095 1.417 0.264 1.641 1.625 2.199 2.025 0.613
66c2a07 2.260 1.019 1.651 0.991 1.298 0.279 1.578 1.592 2.168 1.997 0.595
Lemover

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pull request commentOpenXiangShan/XiangShan

mmu.tlb: ptw resp will refill both ld & st tlb

[Generated by IPC robot] commit: 780ea3523a9a151b10ce4382ca4458b447b358fb

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
780ea35 2.274 1.039 1.537 1.100 1.420 0.265 1.613 1.590 2.211 2.256 0.616

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
ef90f6b 2.258 1.423 0.266 1.613 2.253 0.613
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
c9ebdf9 2.270 1.030 1.530 1.094 1.416 0.264 1.641 1.612 2.200 2.021 0.614
a1ea7f7 2.259 1.029 1.529 1.095 1.417 0.264 1.641 1.625 2.199 2.025 0.613
66c2a07 2.260 1.019 1.651 0.991 1.298 0.279 1.578 1.592 2.168 1.997 0.595
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issue closedOpenXiangShan/XiangShan

The l2miss not connect any pin how to implement PTW

io.dpath.perf.l2miss := false io.dpath.perf.l2hit := false

https://arxiv.org/pdf/2009.07723.pdf -> figurer 1.

The l2miss not connect any pin how to implement figurer 1. PTW

io.dpath.perf.pte_hit out not connect, either

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fatalfeel

issue commentOpenXiangShan/XiangShan

The l2miss not connect any pin how to implement PTW

I'm closing this issue because this is not a rocket-chip repo. Please raise issues at https://github.com/chipsalliance/rocket-chip.

fatalfeel

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pull request commentOpenXiangShan/XiangShan

MissQueue: fix bug in miss-merge logic

[Generated by IPC robot] commit: f0c6502660290ba9869b64da22cbe30d46fc695a

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
f0c6502 2.267 1.041 1.537 1.096 1.420 0.265 1.608 1.599 2.209 2.244 0.614

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commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
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9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
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cc5a5f2 2.276 1.020 1.648 0.990 1.299 0.279 1.570 1.586 2.163 1.994 0.595
linjuanZ

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pull request commentOpenXiangShan/XiangShan

backend,rs: add counters for critical wakeup sources

[Generated by IPC robot] commit: 8471fd8aca8f948178aa00d4dc506cff519cd878

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
8471fd8 2.255 1.039 1.538 1.098 1.422 0.265 1.626 1.632 2.214 2.259 0.618

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
c88c3a2 2.255 1.040 1.537 1.097 1.423 0.266 1.647 1.628 2.210 2.258 0.615
42ba7d8 2.242 1.042 1.537 1.098 1.417 0.266 1.642 1.629 2.211 2.254 0.616
64056be 2.263 1.038 1.535 1.098 1.420 0.266 1.608 1.635 2.202 2.038 0.615
a792bcf 2.267 1.033 1.533 1.098 1.415 0.265 1.600 1.624 2.200 2.018 0.615
59a7cc9 2.256 1.035 1.536 1.098 1.418 0.266 1.624 1.609 2.205 2.039 0.614
9bd9cdf 2.268 1.033 1.529 1.091 1.420 0.264 1.633 1.608 2.193 2.006 0.613
c9ebdf9 2.270 1.030 1.530 1.094 1.416 0.264 1.641 1.612 2.200 2.021 0.614
a1ea7f7 2.259 1.029 1.529 1.095 1.417 0.264 1.641 1.625 2.199 2.025 0.613
66c2a07 2.260 1.019 1.651 0.991 1.298 0.279 1.578 1.592 2.168 1.997 0.595
cc5a5f2 2.276 1.020 1.648 0.990 1.299 0.279 1.570 1.586 2.163 1.994 0.595
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Yinan Xu

commit sha 8471fd8aca8f948178aa00d4dc506cff519cd878

backend,rs: add counters for critical wakeup sources This commit adds critical_wakeup_*_* counters to indicate which function units wake up the instructions in RS. Previously we have wait_for_src_* counters but they cannot represent where the critical operand (the last waiting operand) comes from. We need these counters to optimize fast wakeup logic. If some instructions critically depend on some other instructions, we can think of how we can optimize the wakeup process. Furthermore, this commit also adds a specific counter for FMAs that wakeup other FMAs' third operand. This helps us to decide which strategy is used for FMA fast issue.

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Yinan Xu

commit sha 4f33f661e523bb2b86127226f9933816e3009c19

backend,rs: add counters for critical wakeup sources This commit adds critical_wakeup_*_* counters to indicate which function units wake up the instructions in RS. Previously we have wait_for_src_* counters but they cannot represent where the critical operand (the last waiting operand) comes from. We need these counters to optimize fast wakeup logic. If some instructions critically depend on some other instructions, we can think of how we can optimize the wakeup process.

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backend,rs: add counters for critical wakeup sources

This commit adds critical_wakeup__ counters to indicate which function units wake up the instructions in RS. Previously we have wait_for_src_* counters but they cannot represent where the critical operand (the last waiting operand) comes from.

We need these counters to optimize fast wakeup logic. If some instructions critically depend on some other instructions, we can think of how we can optimize the wakeup process.

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