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Jiawei Lin ljwljwljwljw Institute of Computing Technology, CAS Beijing

ljwljwljwljw/FPU 4

A chisel implementation of IEEE 754 mix-precision RISCV FPU

ljwljwljwljw/rocket-chip 2

Rocket Chip Generator

ljwljwljwljw/api-config-chipsalliance 0

A Scala library for Context-Dependent Evironments

ljwljwljwljw/chisel-testers2 0

Repository for chisel3 testers2 open alpha

ljwljwljwljw/MIPSR10K 0

MIPS R10000 architecture simulator with C++

ljwljwljwljw/NutShell 0

RISC-V SoC designed by students in UCAS

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Merge branch 'l1-l2-com' of github.com:OpenXiangShan/XiangShan into l1-l2-com

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William Wang

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misc: fix alias datapath

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Merge branch 'non-inclusive' into alias

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LinJiawei

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MSHR: fix bugs

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emu.cpp: fix wave-path arg

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LinJiawei

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emu.cpp: compatibility fix

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emu.cpp: compatibility fix
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Merge branch 'l1-l2-com' of github.com:OpenXiangShan/XiangShan into l1-l2-com

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Update 1.txt

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Merge pull request #4 from ljwljwljwljw/ljwljwljwljw-patch-2 Update .mergify.yml

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ci(Mergify): configuration update Signed-off-by: Jiawei Lin <linjiawei20s@ict.ac.cn>

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Merge pull request #2 from ljwljwljwljw/mergify/ljwljwljwljw/config-update ci(Mergify): configuration update

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PR merged ljwljwljwljw/mergify-test

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ci(Mergify): configuration update Signed-off-by: Jiawei Lin <linjiawei20s@ict.ac.cn>

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misc: fix alias datapath (#26)

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