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fwzhang/chisel-testers2 0

Repository for chisel3 testers2 open alpha

fwzhang/chisel3 0

Chisel 3: A Modern Hardware Design Language

fwzhang/gem5 0

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

fwzhang/ohmyzsh 0

🙃 A delightful community-driven (with 1700+ contributors) framework for managing your zsh configuration. Includes nearly 300 optional plugins (rails, git, OSX, hub, capistrano, brew, ant, php, python, etc), over 140 themes to spice up your morning, and an auto-update tool so that makes it easy to keep up with the latest updates from the community.

fwzhang/riscv-binutils-gdb 0

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

fwzhang/riscv-bitmanip 0

Working draft of the proposed RISC-V Bitmanipulation extension

fwzhang/rocket-chip 0

Rocket Chip Generator

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Zhangfw

commit sha 9e3a32bf326a61e5471270a31d092c63352b3e9e

ci: fix bitmanip workload name

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Zhangfw

commit sha aef035c62e1d7bd52d96ea646df61ea7f00176b8

fix fusion instruction target

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PR opened OpenXiangShan/XiangShan

Bmu: support zbk* instruction

This PR add Zbk* instruction to Bmu, but the zext.h is replace by packw. we can enlarge fuoptype for futher more instruction. ci: add Bmu instruction test

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YikeZhou

commit sha e92092e77b5a9868f8c415bf01cbc59fc5b98765

MEFreeList: use tailPtr instead of tailPtrNext in free reg cnt

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YikeZhou

commit sha 62d2a04b2f32541ef7bfc530b15331f1e1d4af9c

backend, rename: optimize MEFreeList free logic

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YikeZhou

commit sha 0153cd55ca4811a69821e72f146368fb37d56d9a

backend, rename: elimination psrc directly from intRat

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zoujr

commit sha 65fddcf0358a85e75e3881fcfda6be033c239922

FTQ: Fix the bug that carry calculation is wrong when generating FTB_entry

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Yinan Xu

commit sha b6c0697a0c89a5087c0388eb533595b98ab9d8d6

backend,rs: add counters for critical wakeup sources (#1027) This commit adds critical_wakeup_*_* counters to indicate which function units wake up the instructions in RS. Previously we have wait_for_src_* counters but they cannot represent where the critical operand (the last waiting operand) comes from. We need these counters to optimize fast wakeup logic. If some instructions critically depend on some other instructions, we can think of how we can optimize the wakeup process. Furthermore, this commit also adds a specific counter for FMAs that wakeup other FMAs' third operand. This helps us to decide which strategy is used for FMA fast issue.

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zhanglinjuan

commit sha c33a770f183944c43e78ddc9dbdd9cc8bb331d2c

MissQueue: fix perf bug when MissQ merges load miss (#1037)

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Yinan Xu

commit sha 93b61a80fde4fea6fa320f74997823b340d24bff

regfile: manually reset every registers (#1038) This commit adds manual reset for every register in Regfile. Previously the reset is done by add reset values to the registers. However, physically general-purpose register file does not have reset values. Since all the regfile always has the same writeback data, we don't need to explicitly assign reset data.

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rvcoresjw

commit sha 8130d625fe80f23bf8edea675fa9909ac95c219f

modify dma bus width form 256 to 128 bits (#1041) * add top IOs * modify dma bus data width from 256 to 128 bits * add top single to SimTop.scala

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JinYue

commit sha efcb3cd399278481f661d6c225dac2322173e8ea

ICache: fix fencei not connected

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JinYue

commit sha 03c39bde52118aaa378ae3818378d8be7603b1f9

ICache: fix physical tag bug * Using get_phy_tag function instead of get_tag * This bug happens when using VIPT ICache and setting lage set number

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Jay

commit sha cf2809cc68f2be16a7493b8584c8a77c8c5503ee

Merge pull request #1044 from OpenXiangShan/fix-fencei Fix fencei and physical tag bugs in ICache

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YikeZhou

commit sha 23304efd33f189dcabda24b4ce68478f09026109

backend, freelist: opt flush process in MEFreeList 1) bug fix: updateArchRefCounter should be related with pdest, not old_pdest 2) remove complicated logic of headPtr recovery when flushing

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YikeZhou

commit sha 5036675628140f3d0e72ff7be40cde231cf3f653

Merge branch 'master' into me-timing

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zfw

commit sha 5092a2981be3bf139d23da5f6ba9478e83fbf4e6

ci: update RV64GCB workloads (#1047) This PR replaces coremark, microbench, and all perfromence test workloads by corresponding RV64GCB workloads.

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Yinan Xu

commit sha ebb8ebf8de8980aaa030b36655a892812f423b9d

core: add timer counters for important stages (#1045) This commit adds timer counters for some important pipeline stages, including rename, dispatch, dispatch2, select, issue, execute, commit. We add performance counters for different types of instructions to see the latency in different pipeline stages.

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YikeZhou

commit sha 8949e3b057b227c5ccfac60e56692b5950a79fc7

backend, freelist: modify free list allocatePhyReg logic 1) generate ptr and preg in a vec first 2) use renameEnable to replace common parts in allocating logic

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YikeZhou

commit sha 20acd4aecd21b8d45db5ce6ef2e2450d6e0b2271

backend, freelist: remove unused log & assertions

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Yinan Xu

commit sha 7bb7bf3de0c525026314e06414d090b49141171e

backend,rs: load balance for issue selection (#1048) This commit adds load balance strategy in issue selection logic for reservation stations. Previously we have a load balance option in ExuBlock, but it cannot work if the function units have feedbacks to RS. In this commit it is removed. This commit adds a victim index option for oldestFirst. For LOAD, the first issue port has better performance and thus we set the victim index to 0. For other function units, we use the last issue port.

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Yinan Xu

commit sha 65e2f311b437372e21f9eafd7e72585e0b3a431f

rs, fma: separate fadd and fmul issue (#1042) This commit splits FMA instructions into FMUL and FADD for execution. When the first two operands are ready, an FMA instruction can be issued and the intermediate result will be written back to RS after two cycles. Since RS currently has DataArray to store the operands, we reuse it to store the intermediate FMUL result. When an FMA enters deq stage and leaves RS with only two operands, we mark it as midState ready at this clock cycle T0. If the instruction's third operand becomes ready at T0, it can be selected at T1 and issued at T2, when FMUL is also finished. The intermediate result will be sent to FADD instead of writing back to RS. If the instruction's third operand becomes ready later, we have the data in DataArray or at DataArray's write port. Thus, it's ok to set midState ready at clock cycle T0. The separation of FMA instructions will increase issue pressure since RS needs to issue more times. However, it larges reduce FMA latency if many FMA instructions are waiting for the third operand.

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YikeZhou

commit sha 802dc347f22e8f5401555a09cde6138c78b85b17

backend, freelist: simplify walk logic

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Zhangfw

commit sha 63ece202f498c4eb3deba68b0e7061c28e9d57c1

ci: add zbk* instruction test

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Zhou Yaoyang

commit sha 5070700454a51c35af4b548f8892c7f1f5b7d022

Adding GEM5 utils

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Zhangfw

commit sha 903d1cd2335f7a78beb35954d7e414e2abb0b788

Merge branch 'master' of github.com:OpenXiangShan/NEMU

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Zhangfw

commit sha 0df2fa9cacb478d91e0fddd9d0b3649c4d029eb2

support zbk* instructions

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Zhangfw

commit sha e3aa13cb786e4804985af4c88aba1af53677a8cc

fix filename and pathname

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PR opened OpenXiangShan/XiangShan

ci: replace rv64gc workloads by rv64gcb workloads

This PR replace coremark, microbench, and all perfromence test workloads by corresponding rv64gcb workloads.

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PR opened OpenXiangShan/XiangShan

alu, decode: fix alu instruction and change instruction name
  • Alu: fix andn, orn, xnor
  • Decode: change instruction name
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Zhangfw

commit sha 074caec8fe4966a039c9ae3eabae2b3277f0485d

fix adduw

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PullRequestReviewEvent

PR opened OpenXiangShan/XiangShan

Alu: optimize timing for Bitmanip

This pull request optimize timing by adding a 32bit adder for addw and changing the encode.

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Yinan Xu

commit sha 9bc8f3e1310a1cfce8346e8d2194b70e425a93e4

rs,age: optimize timing for output (#970) This commit changes how io.out is computed for age detector. We use a register to keep track of the position of the oldest instruction. Since the updating information has better timing than issue, this could optimize the timing of issue logic.

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Yinan Xu

commit sha 605f31fcbd79a7dd92bcb43ce3c17ea6dc1f5717

rs,bypass: add left and right bypass strategy (#971) * rs,bypass: remove optBuf for valid bits * rs,bypass: add left and right bypass strategy This commit adds another bypass network implementation to optimize timing of the first stage of function units. In BypassNetworkLeft, we bypass data at the same cycle that function units write data back. This increases the length of the critical path of the last stage of function units but reduces the length of the critical path of the first stage of function units. Some function units that require a shorter stage zero, like LOAD, may use BypassNetworkLeft. In this commit, we set all bypass networks to the left style, but we will make it configurable depending on different function units in the future.

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Lemover

commit sha 5854c1ed5b0edc307f0bd863fd2dc140f5221006

l2tlb: mem access now takes 512 bits, 8 ptes (#973) * mmu: wrap l2tlb's param withL2TLBParameters * mmu.l2tlb: add param blockBytes: 64, 8 ptes * mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096 * mmu.l2tlb: add config print * mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

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Jiawei Lin

commit sha c21bff99db38ffd5df19a9459a048e16b7b7cb23

Bump chisel to 3.5 (#974) * bump chisel to 3.5 * Remove deprecated 'toBool' && disable tl monitor * Update RocketChip / Re-enable TLMonitor * Makefile: remove '--infer-rw'

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Jiawei Lin

commit sha dd81f7f0d64979278531c2b42e780c54af9d2e3f

bump difftest: use clang to compile verialted files (#976)

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Yinan Xu

commit sha dd3815946863fc2bb2e774fd6e871f2f3f7d07ce

backend,exu: connect writeback when possible (#977) This commit optimizes ExuBlock timing by connecting writeback when possible. The timing priorities are RegNext(rs.fastUopOut) > fu.writeback > arbiter.out(--> io.rfWriteback --> rs.writeback). The higher priority, the better timing. (1) When function units have exclusive writeback ports, their wakeup ports for reservation stations can be connected directly from function units' writeback ports. Special case: when the function unit has fastUopOut, valid and uop should be RegNext. (2) If the reservation station has fastUopOut for all instructions in this exu, we should replace io.fuWriteback with RegNext(fastUopOut). In this case, the corresponding execution units must have exclusive writeback ports, unless it's impossible that rs can ensure the instruction is able to write the regfile. (3) If the reservation station has fastUopOut for all instructions in this exu, we should replace io.rfWriteback (rs.writeback) with RegNext(rs.wakeupOut).

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Zhangfw

commit sha 3695f96dc2965b23a8cb0e6dc2fadd32156a4943

Merge remote-tracking branch 'origin/master' into bitmanip-1.0

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PR opened OpenXiangShan/XiangShan

Bitmanip 1.0
  • separate the Alu instructions by 64bit data instructions and w-suffix instructions
  • optimize select logic of instructions result
+163 -155

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zfw

commit sha ee8ff153da78c0e2933b0e53d29a7f40ba42ccc1

Support RISC-V bitmanip extension v1.0 (#919) * Add bitmanip v1.0 instructions into decede table * Fix some instructions' name * Add basic instructions into Alu * Add clz, ctz, cpop, clmul Instruction into MulDivExeUnit

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wakafa

commit sha 4f0a2459f8695dd8c31edd6c0ca4d6b04040d007

top: dump graphml, plusArgs and dts in json type (#917)

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Yinan Xu

commit sha a4a566af3d56be7c8089639a5d2e72255864d875

github,ci: increase timeout limit (#926)

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Yinan Xu

commit sha 59bcbb59321927f518389a53c0eaf8a58a2531e5

scripts: add random seed to emu runs (#925)

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lqre

commit sha d4aca96cccdcdafa80dd344996e18d1978a01af7

core: add basic debug mode features (#918) Basic features of debug mode are implemented. * Rewrite CSR for debug mode * Peripheral work for implementing debug module * Added single step support * Use difftest with JTAG support

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Yinan Xu

commit sha cef43b8fa2ccaf73276fc9542538731b0e2a189d

Bump difftest to fix multicore simulation (#929) Multi-core Linux can boot now, again.

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YikeZhou

commit sha 8b8e745d3f08bd9c4a2bf803d2227e9ef420422e

backend, rename: support move elimination (#920) * Bundle, Rename: Add some comments FreeList, RenameTable: Comment out unused variables * refcnt: Implement AdderTree for reference counter * build.sc: add testOne method for unit test * AdderTest: add testbench for Adder (passed) * AdderTree: Add testbench for AdderTree (passed) * ReferenceCounter: implement a 2-bit counter * Rename: remove redundant code * Rename: prepared for move elimination [WIP] * Roq: add eliminated move bit in roq entry; label elim move inst as writebacked AlternativeFreeList: new impl for int free list Rename: change io of free list Dispatch1: (todo) not send move to intDq Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio ReferenceCounter: add debug print msg * Dispatch1: [BUG FIX] not send move inst to IntDq * DecodeUnit: [BUG FIX] differentiate li from mv * Bug fix: 1. Dispatch1: should not label pdest of move as busy in busy table 2. Rename: use psrc0 to index bit vec isMax 3. AlternativeFreeList: fix maxVec calculation logic and ref counter increment logic Besides, more debug info and assertions were added. * AlternativeFreeList Bug Fix: 1. add redirect input - shouldn't allocate reg when redirect is valid 2. handle duplicate preg in roqCommits in int free list * AlternativeFreeList: Fix value assignment race condition * Rename: Fix value assignment race condition too * RenameTable: refactor spec/arch table write process * Roq: Fix debug_exuData of move(addi) instruction (it was trash data before because move needn't enter exu) * Rename: change intFreeList's redirect process (by setting headPtr back) and flush process * ME: microbench & coremark & linux-hello passed 1. DecodeUnit: treat `mv x,x` inst as non-move 2. AlternativeFreeList: handle duplicate walk req correctly 3. Roq: fix debug_exuData bug (make sure writeback that updates debug_exuData happens before ME instruction in program order) * AlternativeFreeList: License added build.sc: remove unused config Others: comments added * package rename: remove unused modules * Roq: Replace debug_prf with a cleaner fix method * Disp1/AltFL/Rename: del unnecessary white spaces * build.sc: change stack size AlternativeFreeList: turn off assertions * build.sc: change stack size for test

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Lemover

commit sha 149086ea0cc093ec09cfe57cff75bd37c35dbff6

mmu.l2tlb: cut down l2tlb.l2 size to 256 and set l2tlb.l3 way to 8, keep l3's size (#927) * Miniconfig: change dtlb size to 32 at minimal config * mmu.dtlb: change tlb's replacement access code style dtlb now can support plru (functionaly). plru with multi-access is chained, so there will be long latency for dtlb to use plru. * mmu.l2tlb: cut down l2tlb.l2 to 256 and set l3.way to 8 * mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096 * Revert "mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096" This reverts commit efbb077ef4be1d4e585a49537ba9be3144423b52.

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Yinan Xu

commit sha 85b4cd5424d4dea59dc60341a4fd0178a0a49676

backend: separate store address and data (#921) This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue.

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lqre

commit sha 096d1aa8173351fc6d1d490611a880ad070673aa

difftest: disable jtag remote bitbang server as default (#938) * Use difftest version that auto diables jtag rbb server Use newer difftest version so that jtag remote bitbang server is automatically disabled. Use --enable-jtag to enable.

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Lemover

commit sha 5aae5b8dd522c46434b81201cec5dcbf1bd28e4d

l0tlb: add a new level tlb to each mem pipeline (#936) * Miniconfig: change dtlb size to 32 at minimal config * mmu.dtlb: change tlb's replacement access code style dtlb now can support plru (functionaly). plru with multi-access is chained, so there will be long latency for dtlb to use plru. * mmu.tlb: add tlb at new level named btlb bridge tlb: one l0-tlb in each mem pipeline all the l0-tlb connect to bridge tlb btlb connects to l2tlb, so btlb is also l1-tlb itlb remains the same * mmu.tlb: set tlb size: l0-8, l1-64 * mmu.btlb: add sfence logic * mmu.tlb: fix bug of sfence logic of g bit * mmu.btlb: add some perf counter * mmu.btlb: fix bug of random replace * mmu.filter: add port vector to record which ports the reqs come from * mmu.btlb: add some perf counter && add refill mask * mmu.filter: add check for flushed req

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Yinan Xu

commit sha ba8c0d5ed431aa7a40ff0d44dc233623a1aa7db2

backend, rs: add a maximum dequeue width (default 2) (#935) This commit limits dequeue width of every RS to 2 for better timing.

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YikeZhou

commit sha d3975bec0d92e7bc1c2facaaef77098ebee885a0

backend, rename: performance bug fixed in move elimination process (#934) * Rename: add perf counter for move elimination [NOTE] There are three reasons why one ME is cancelled: 1. counter reaching max value 2. RAW dependency with former instruction 3. 2 move instruction with same psrc in 1 cycle * Rename: add debug log + fix perf bug for move elim cancelation * AlternativeFreeList: parameterize width of counter * Rename:[bug fix] RAW conflict in meEnable decision (suppose former inst=i while latter inst=j, i does not have to be move instruction)

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Yinan Xu

commit sha 34868f53662ea778c804a4ea385b95775aa753dd

github,ci: use head commit hash for perf data (#941)

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Lemover

commit sha b052b97230d6fdeedaf4e4905092adef6e768b4f

Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945) This reverts commit 5aae5b8dd522c46434b81201cec5dcbf1bd28e4d.

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Yinan Xu

commit sha 1a0f06ee6669d8d336929ef6728eceb5b9e125d5

exu: add suggestName to function units (#944)

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Yinan Xu

commit sha 90923bd321b424b966a00564ec7547c55884d76e

backend, rs: add an age matrix to find the oldest instruction (#937) * backend, rs: add an age matrix to find the oldest instruction This commit adds an age matrix to reservation station to find the oldest instruction. This enables the RS to schedule the oldest instruction first. This commit also adda performance counter for oldest inst

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Lemover

commit sha c266a93b34b5a4da322104b0f151a48de3db4d60

mmu.tlb: rasie exception to update a/d (#928) * Miniconfig: change dtlb size to 32 at minimal config * mmu.dtlb: change tlb's replacement access code style dtlb now can support plru (functionaly). plru with multi-access is chained, so there will be long latency for dtlb to use plru. * mmu.tlb: raise pf to update a/d * fp: fix bug of ieee NaN multiple results * CSR: fix bug of not clearing mprv at mret when mpp is M

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Yinan Xu

commit sha 01a527611700171b858a2e13dcbfe5af3b0bbede

github,ci: use action id for perf data filename (#951) This commit changes how performance data file is named. Previously we use GITHUB_SHA or pull_request.head.sha. However, we cannot easily get the sha or they do not work for master branch.

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Yinan Xu

commit sha 233f4fd3399a5d283cf809312c2d60af544dfcd4

backend: change the second regfile to 6R8W (#950) This commit changes how to organize reservation stations in the second ExuBlock. Now the second ExuBlock accepts MUL, MUL, STD, STD. The int regfile in this ExuBlock becomes 6R8W.

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Zhangfw

commit sha 3230ea2dd1d208d66f454f4387f59dfdff6813d5

Kconfig: Add RVB Option

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Zhangfw

commit sha 931d8b44d43aae793bd9853868fd1257836e7d11

Add RVB support

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Zhangfw

commit sha bd94cfc1103be0f570ea44af09167356b19bffd2

decode: fix decode partten

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Zhangfw

commit sha b99b3046643cf784395f5326e401513500343b3b

bitmanip: fix imm

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Zhangfw

commit sha fd7fe66c73cc16fc19d04475ac4580f858192266

Kconfig: resolve conflict

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zfw

commit sha b46de67b54212c5f22804a3022ef7eb9e91a2751

Merge pull request #23 from OpenXiangShan/bitmanip-1.0 Add RVB support

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PR merged OpenXiangShan/NEMU

Bitmanip 1.0

Add RISC-V Bitmanip support

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Yinan Xu

commit sha 7ac94df7739be38cf1b54cbac9e5529c36195fec

difftest: re-add multi-core difftest APIs (#24) * `difftest_set_mhartid` * `difftest_put_gmaddr` Originally implemented by wakafa

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ZhangZifei

commit sha 19bc39bed255d896aa9e8aa39799558e85e60127

rv64.mmu: raise exception to update a/d

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ZhangZifei

commit sha 689770594aa84d4bbdbaa759025223b4364dca89

rv64.fp: update mstatus.sd immediately when as ref

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ZhangZifei

commit sha f8138ce2da11c877632bb5be231fd302d897b0d2

mmu: comment some log

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ZhangZifei

commit sha 46586dd8c8e0b462972c5d5293ba18dc7d4826ee

mmu: wrap 'update a/d by software' with CONFIG_SHARE

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ZhangZifei

commit sha 8ae08a454b306199768890f7d149883f0b763cee

Merge remote-tracking branch 'origin/master' into tlb_ad_excep

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William Wang

commit sha 2a15dae2f323c5d76cb0e686dcefd22a496192c5

Merge pull request #25 from OpenXiangShan/tlb_ad_excep mmu: raise exception to update a/d when as ref

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Zhangfw

commit sha fd7fe66c73cc16fc19d04475ac4580f858192266

Kconfig: resolve conflict

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bitmanip: fix imm

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Bitmanip 1.0

Add RISC-V Bitmanip support

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