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《计算机体系结构(第2版)》课后习题

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Lipsi: Probably the Smallest Processor in the World

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My vegetable exploded.

PR opened OpenXiangShan/XiangShan

backend, freelist: optimize critical path & verilog code size in MEFreeList
  1. optimize free/allocate/walk/flush logic in MEFreeList
  2. remove useless assertions
  3. decrease length of generated verilog file
+61 -148

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zoujr

commit sha 65fddcf0358a85e75e3881fcfda6be033c239922

FTQ: Fix the bug that carry calculation is wrong when generating FTB_entry

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zfw

commit sha 5092a2981be3bf139d23da5f6ba9478e83fbf4e6

ci: update RV64GCB workloads (#1047) This PR replaces coremark, microbench, and all perfromence test workloads by corresponding RV64GCB workloads.

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Yinan Xu

commit sha ebb8ebf8de8980aaa030b36655a892812f423b9d

core: add timer counters for important stages (#1045) This commit adds timer counters for some important pipeline stages, including rename, dispatch, dispatch2, select, issue, execute, commit. We add performance counters for different types of instructions to see the latency in different pipeline stages.

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Yinan Xu

commit sha 7bb7bf3de0c525026314e06414d090b49141171e

backend,rs: load balance for issue selection (#1048) This commit adds load balance strategy in issue selection logic for reservation stations. Previously we have a load balance option in ExuBlock, but it cannot work if the function units have feedbacks to RS. In this commit it is removed. This commit adds a victim index option for oldestFirst. For LOAD, the first issue port has better performance and thus we set the victim index to 0. For other function units, we use the last issue port.

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Yinan Xu

commit sha 65e2f311b437372e21f9eafd7e72585e0b3a431f

rs, fma: separate fadd and fmul issue (#1042) This commit splits FMA instructions into FMUL and FADD for execution. When the first two operands are ready, an FMA instruction can be issued and the intermediate result will be written back to RS after two cycles. Since RS currently has DataArray to store the operands, we reuse it to store the intermediate FMUL result. When an FMA enters deq stage and leaves RS with only two operands, we mark it as midState ready at this clock cycle T0. If the instruction's third operand becomes ready at T0, it can be selected at T1 and issued at T2, when FMUL is also finished. The intermediate result will be sent to FADD instead of writing back to RS. If the instruction's third operand becomes ready later, we have the data in DataArray or at DataArray's write port. Thus, it's ok to set midState ready at clock cycle T0. The separation of FMA instructions will increase issue pressure since RS needs to issue more times. However, it larges reduce FMA latency if many FMA instructions are waiting for the third operand.

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Steve Gou

commit sha aa9d86a61d5bbe13ec6464186ede1466421be1e7

Merge pull request #1036 from OpenXiangShan/false_hit_fix FTQ: Fix the false hit bug when run mcf

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Yinan Xu

commit sha d8798cc89aca40139df98827bd8cdc8f700dc8c6

backend: add performance counters for first issue (#1050) This commit adds performance counters for function units that have feedback to reservation stations, including FMA, Load and Store. We add performance counters to show how many instructions are issued for multiple times.

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YikeZhou

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Merge branch 'master' into me-timing

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YikeZhou

commit sha c63125be60df2479349dd642281ef340ef945d5c

backend, freelist: shrink verilog size by using scala variable instead of chisel var in MEFreeList.scala

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YikeZhou

commit sha 802dc347f22e8f5401555a09cde6138c78b85b17

backend, freelist: simplify walk logic

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YikeZhou

commit sha 8949e3b057b227c5ccfac60e56692b5950a79fc7

backend, freelist: modify free list allocatePhyReg logic 1) generate ptr and preg in a vec first 2) use renameEnable to replace common parts in allocating logic

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YikeZhou

commit sha 20acd4aecd21b8d45db5ce6ef2e2450d6e0b2271

backend, freelist: remove unused log & assertions

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William Wang

commit sha 103b691438e3afd99c245eed144b9149ff7c61ef

mem: reduce refill writeback delay by 1 cycle * Now inst being refilled currently can be selected as wb candidate

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William Wang

commit sha 594ba8ac93360d08b5da8cc83597e39f211db3fe

mem: let lq refill width be equal to l1d bus width

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William Wang

commit sha 7ab59370ffc775aed60862417b6a48af7db40b5f

chore: update load_miss_penalty_to_use counter

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William Wang

commit sha 63d95f38401521cb24e7e3507328484614c958c3

ci: run ci on fastpath (without master)

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William Wang

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Merge remote-tracking branch 'origin/master' into fastpath

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William Wang

commit sha 58628cdc809320a90f350988df672d2179a33ade

Merge branch 'fastpath' into fastpath-ci

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William Wang

commit sha aaf9f60c9dc48ff7384d5405a2b0b84d80519368

dcache: fix refill when merge refill request Update should_refill_data eariler to refill first half of refill data

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William Wang

commit sha 99aa3a7e43199cc4e00eb7165e0a075d2e409f2b

difftest: bump version to support clang

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William Wang

commit sha 16ce2b800c039b7c80e33f6a528faba880e52345

Revert "ci: run ci on fastpath (without master)" This reverts commit 63d95f38401521cb24e7e3507328484614c958c3.

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William Wang

commit sha b603de6077afcb821dd6b366b60e253e4b2dc3e2

Merge remote-tracking branch 'origin/master' into fast-refill

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William Wang

commit sha 588e93e03b231b74ac1dae8651cc63b28d07b301

chore: fix frontend / memblock merge conflict

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Lingrui98

commit sha 3bcae573fc6ed87eb736b42d2ac60f1adc0959d1

ftq: modify jmpTarget in FtbEntry whenever jalr target changes * previously we only modify jmpTarget on misprediction, and that's because we only use ftb to predict jalr target. However, with the presence of an indirect branch predictor, there exists such case that an indirect branch is correctly predicted when the target in ftb entry is wrong.

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Guokai Chen

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frontend: add ittage indirect predictor

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Lingrui98

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bundle: add a full target in update bundle

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Guokai Chen

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frontend: ittage fix update valid condition

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Lingrui98

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bundle: add a full target in update bundle

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Guokai Chen

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frontend: ittage: switch to full length jmp target

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Steve Gou

commit sha 1c8d55c9066bf94c47305e2d396b9c93512323c5

Merge pull request #992 from OpenXiangShan/decoupled-frontend-indirect frontend: add ittage indirect predictor

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William Wang

commit sha b460b7e4c6a6eeb8c959024a15c44273fd41063b

Merge remote-tracking branch 'origin/master' into fast-refill

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Lingrui98

commit sha ba4cf51546af7ae0ff7fbef3207618f7f32b2c4f

parameters: ras size 32, btb size 4096

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YikeZhou

commit sha 23304efd33f189dcabda24b4ce68478f09026109

backend, freelist: opt flush process in MEFreeList 1) bug fix: updateArchRefCounter should be related with pdest, not old_pdest 2) remove complicated logic of headPtr recovery when flushing

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YikeZhou

commit sha 31ebfb1dd00f6473404eca1f5d9153cc53e133a7

backend, rename: support elimination of move instruction whose lsrc is 0 + bug fix (#1008) * backend, rename: support elimination of mv inst whose lsrc=0 [known bug] instr page fault not properly raised after sfence.vma * backend, roq: [bug fix] won't label me with exception as writebacked

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PR merged OpenXiangShan/XiangShan

backend, rename: support elimination of move instruction whose lsrc is 0 + bug fix

new feature: instructions like mv foo,x0 or li foo,0 can be eliminated now.

bug fix: when eliminated move instruction enters roq, if there already exists valid bit in exceptionVec, then it shouldn't be labeled writebacked immediately.

Next: optimize verilog code length & timing

+30 -29

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PR opened OpenXiangShan/XiangShan

backend, rename: support elimination of move instruction whose lsrc is 0 + bug fix

new feature: instructions like mv foo,x0 or li foo,0 can be eliminated now.

bug fix: when eliminated move instruction enters roq, if there already exists valid bit in exceptionVec, then it shouldn't be labeled writebacked immediately.

Next: optimize verilog code length & timing

+30 -29

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commit sha b77110180c268f83153bdad50ab44d062dea548d

backend, roq: [bug fix] won't label me with exception as writebacked

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commit sha 6e3cddfe588ea01af869549161ffcd8ac18a76f5

AlternativeFreeList: parameterize length of FL FreeList: same as above Parameters: add 2 core param and 2 derived param [TODO] use EnableIntMoveElim to control ME function

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YikeZhou

commit sha 39d3280eb31ef056506ae9fdaa3982f76a903ba7

rename: [refactor] move free list into 'freelist' package "trait" was used to improve code style parameters: use EnableIntMoveElim to control code generation [WIP] EnableIntMoveElim=false hasn't been tested

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YikeZhou

commit sha 5eb4af5ba4d9ec70191944b8386c8983f355d751

rename/roq/dispatch1: support EnableIntMoveElim=false (finish refactoring) [TODO] remove useless code

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YikeZhou

commit sha 2824417d2e22b2c4ee5cdb3f1ad0a33680492666

rename: [refactoring] remove useless file + comment added

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YikeZhou

commit sha f6c0bbe7c6b93499f5bf81cda34d7af90eb81e5d

AlternativeFreeList: fix flush bug with headPtrNext (when counting duplicate reg ref, subtracting cmtCnt from archRefCnt is needed)

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YikeZhou

commit sha 92cb400d0378fac8ef8d688133650b9c8938ce55

Merge branch 'rename-flush-bug-fix' into me-opt

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YikeZhou

commit sha 73c4359ef65acf2a13c3464140d2475b49de1e5b

rename: handle mv inst with ldest=0 or ldest=lsrc decode: slightly change def of `isMove` [TODO] handle mv inst with lsrc=0

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YikeZhou

commit sha 90f13a3a9a58826a037c698837f5d29508a9c668

MEFreeList: replace "+" with "+&" in reduceTree

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YikeZhou

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Merge branch 'master' into me-opt

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YikeZhou

commit sha 4efb89cb343e36759500991b38d91fa405bbb8ba

Rename: fix doAllocate logic in refactored version MEFreeList: remove useless code + give specified (instead of DontCare) value to phy reg allocated port

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YikeZhou

commit sha a260c31a4329938f9b3de2aa75defe326d5959c3

Merge pull request #949 from OpenXiangShan/me-opt backend, rename: configurable free list & `headPtr` bug fix & `dst=0/dst=src` move inst elimination

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Reviewers
backend, rename: configurable free list & `headPtr` bug fix & `dst=0/dst=src` move inst elimination

New core parameters:

  EnableIntMoveElim: Boolean = true,
  IntRefCounterWidth: Int = 2,

which leads to params in trait HasXSParameter:

  val EnableIntMoveElim = coreParams.EnableIntMoveElim
  val IntRefCounterWidth = coreParams.IntRefCounterWidth
  val StdFreeListSize = NRPhyRegs - 32
  val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 }

With these params you will be able to

  • turn off Move Elimination feature by setting EnableIntMoveElim to false
  • easily evaluate performance under different reference counter width

New package freelist includes 4 source files:

  1. FreeListBaseIO.scala: ports shared by 2 free lists
  2. MEFreeListIO.scala: trait MEFreeListIO extends FreeListBaseIO with additional ports needed by move elimination
  3. StdFreeList.scala: free list of standard type; new version of FreeList
  4. MEFreeList.scala: new version of AlternativeFreelist

Deprecated files AlternativeFreelist.scala and FreeList.scala in package rename were removed.

+434 -366

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YikeZhou

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pull request commentOpenXiangShan/XiangShan

backend, rename: configurable free list & `headPtr` bug fix & `dst=0/dst=src` move inst elimination

When a pipeline flush happened, we need to move headPtr back so that distanceBetween(tailPtr, headPtr) + distinctReg(arch_rat_values) = NRPhyRegs Number of duplicate regs in arch_rat should be calculated as below:

val dupRegVec = WireInit(VecInit(archRefCounter.zip(cmtCounter).map{ case (a, c) => a - c }))
dupRegVec.reduceTree(_ + _)

As this may bring significant delay, further optimization is needed for sure.

with this bug fixed

YikeZhou

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PR closed OpenXiangShan/XiangShan

backend, freelist: fix headPtrNext value when flushing

When a pipeline flush happened, we need to move headPtr back so that distanceBetween(tailPtr, headPtr) + distinctReg(arch_rat_values) = NRPhyRegs Number of duplicate regs in arch_rat should be calculated as below:

val dupRegVec = WireInit(VecInit(archRefCounter.zip(cmtCounter).map{ case (a, c) => a - c }))
dupRegVec.reduceTree(_ + _)

As this may bring significant delay, further optimization is needed for sure.

+3 -2

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YikeZhou

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Pull request review commentOpenXiangShan/XiangShan

backend, freelist: fix headPtrNext value when flushing

 class AlternativeFreeList(implicit p: Parameters) extends XSModule with HasCircu    /*   Flush: directly flush reference counter according to arch-rat-  - replace specRefCounter with archRefCounter; reset headPtr to [ tailPtr - (NRPhyRegs-32) - archRefCounter.reduce(_ + _) ]+  - replace specRefCounter with archRefCounter; reset headPtr to [ tailPtr - (NRPhyRegs-32) - (archRefCounter(i) - cmtCounter(i)).reduce(_ + _) ]    */     // update tail pointer   val tailPtrNext = Mux(io.walk, tailPtr, tailPtr + PopCount(freeVec))   // update head pointer-  val headPtrNext = Mux(io.flush, tailPtr - (NRPhyRegs-32).U - archRefCounter.reduceTree(_ + _), // FIXME Maybe this is too complicated?+  val dupRegVec = WireInit(VecInit(archRefCounter.zip(cmtCounter).map{ case (a, c) => a - c }))+  val headPtrNext = Mux(io.flush, tailPtr - (NRPhyRegs-32).U - dupRegVec.reduceTree(_ + _), // FIXME Maybe this is too complicated?

added in PR #949

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YikeZhou

commit sha 4efb89cb343e36759500991b38d91fa405bbb8ba

Rename: fix doAllocate logic in refactored version MEFreeList: remove useless code + give specified (instead of DontCare) value to phy reg allocated port

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Jiawei Lin

commit sha 28c167e9babff0a625ced1f4598a08fbec28db05

Dcache: convert one hot replace way into uint (#956)

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Yinan Xu

commit sha 1a2cf1521d2269374286d137546263e946c0fc7c

l2, core: add more performance counters (#942) * Refactor print control transform * Adda tilelink bus pmu * Add performance counters for dispatch, issue, execute stages * Add more counters in bus pmu * Insert BusPMU between L3 and L2 * add some TMA perfcnt Co-authored-by: LinJiawei <linjiawei20s@ict.ac.cn> Co-authored-by: William Wang <zeweiwang@outlook.com> Co-authored-by: wangkaifan <wangkaifan@ict.ac.cn>

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Jay

commit sha 0a6329f19c2bd50332f7a2af686ebb8ed9b2010b

Bump difftest submodule (#953) * use --enable-fork option to open lightSSS when running emu * EMU_THREADS(>1) and EMU_TRACE should be set before compiling if using lightSSS * move lightSSS config to difftest/config/config.h

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zfw

commit sha 184a195889c871432da1d39e2885d0af812be3fe

Alu: optimize timing for bitmanip (#959) * separate the Alu instructions by 64bit data instructions and w-suffix instructions * optimize select logic of instructions result

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Yinan Xu

commit sha c92d58b78bb9249da496b3e07ec7346f213c4368

exu: directly connect data from fu if possible (#954) This commit adds support for directly connecting data from function units if the function units exclusively own the writeback ports. This happens for ALU and FMA currently.

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Yinan Xu

commit sha f83b578a214330d722df8637beb76563f3d72811

backend,fu: allow early arbitration via fastUopOut (#962) This commit adds a fastUopOut option to function units. This allows the function units to give valid and uop one cycle before its output data is ready. FastUopOut lets writeback arbitration happen one cycle before data is ready and helps optimize the timing. Since some function units are not ready for this new feature, this commit adds a fastImplemented option to allow function units to have fastUopOut but the data is still at the same cycle as uop. This option will delay the data for one cycle and may cause performance degradation. FastImplemented should be true after function units support fastUopOut.

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Yinan Xu

commit sha 38683dba801f57bc5ea01ce5c9e2d9e220ec7957

rs,age: use less registers for age matrix (#964) This commit reduces register usage in age detector via using the upper matrix only. Since the age matrix is symmetric, age(i)(j) equals !age(j)(i). Besides, age(i)(i) is the same as valid(i). Thus, we also remove validVec in this commit.

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Yinan Xu

commit sha 9bc8f3e1310a1cfce8346e8d2194b70e425a93e4

rs,age: optimize timing for output (#970) This commit changes how io.out is computed for age detector. We use a register to keep track of the position of the oldest instruction. Since the updating information has better timing than issue, this could optimize the timing of issue logic.

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Yinan Xu

commit sha 605f31fcbd79a7dd92bcb43ce3c17ea6dc1f5717

rs,bypass: add left and right bypass strategy (#971) * rs,bypass: remove optBuf for valid bits * rs,bypass: add left and right bypass strategy This commit adds another bypass network implementation to optimize timing of the first stage of function units. In BypassNetworkLeft, we bypass data at the same cycle that function units write data back. This increases the length of the critical path of the last stage of function units but reduces the length of the critical path of the first stage of function units. Some function units that require a shorter stage zero, like LOAD, may use BypassNetworkLeft. In this commit, we set all bypass networks to the left style, but we will make it configurable depending on different function units in the future.

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Lemover

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l2tlb: mem access now takes 512 bits, 8 ptes (#973) * mmu: wrap l2tlb's param withL2TLBParameters * mmu.l2tlb: add param blockBytes: 64, 8 ptes * mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096 * mmu.l2tlb: add config print * mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

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Jiawei Lin

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Bump chisel to 3.5 (#974) * bump chisel to 3.5 * Remove deprecated 'toBool' && disable tl monitor * Update RocketChip / Re-enable TLMonitor * Makefile: remove '--infer-rw'

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Yinan Xu

commit sha 34868f53662ea778c804a4ea385b95775aa753dd

github,ci: use head commit hash for perf data (#941)

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Lemover

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Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945) This reverts commit 5aae5b8dd522c46434b81201cec5dcbf1bd28e4d.

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Yinan Xu

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exu: add suggestName to function units (#944)

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Yinan Xu

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backend, rs: add an age matrix to find the oldest instruction (#937) * backend, rs: add an age matrix to find the oldest instruction This commit adds an age matrix to reservation station to find the oldest instruction. This enables the RS to schedule the oldest instruction first. This commit also adda performance counter for oldest inst

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Lemover

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mmu.tlb: rasie exception to update a/d (#928) * Miniconfig: change dtlb size to 32 at minimal config * mmu.dtlb: change tlb's replacement access code style dtlb now can support plru (functionaly). plru with multi-access is chained, so there will be long latency for dtlb to use plru. * mmu.tlb: raise pf to update a/d * fp: fix bug of ieee NaN multiple results * CSR: fix bug of not clearing mprv at mret when mpp is M

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Yinan Xu

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github,ci: use action id for perf data filename (#951) This commit changes how performance data file is named. Previously we use GITHUB_SHA or pull_request.head.sha. However, we cannot easily get the sha or they do not work for master branch.

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Yinan Xu

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backend: change the second regfile to 6R8W (#950) This commit changes how to organize reservation stations in the second ExuBlock. Now the second ExuBlock accepts MUL, MUL, STD, STD. The int regfile in this ExuBlock becomes 6R8W.

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AlternativeFreeList: fix flush bug with headPtrNext (when counting duplicate reg ref, subtracting cmtCnt from archRefCnt is needed)

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YikeZhou

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rename: handle mv inst with ldest=0 or ldest=lsrc decode: slightly change def of `isMove` [TODO] handle mv inst with lsrc=0

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MEFreeList: replace "+" with "+&" in reduceTree

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issue commentOpenXiangShan/XiangShan

请教一个关于renametable的问题

现在其实是不会再有这种情况

我也是这样理解的。

daxxyy123

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PR opened OpenXiangShan/XiangShan

backend, freelist: fix headPtrNext value when flushing

When a pipeline flush happened, we need to move headPtr back so that distanceBetween(tailPtr, headPtr) + distinctReg(arch_rat_values) = NRPhyRegs Number of duplicate regs in arch_rat should be calculated as below:

val dupRegVec = WireInit(VecInit(archRefCounter.zip(cmtCounter).map{ case (a, c) => a - c }))
dupRegVec.reduceTree(_ + _)

As this may bring significant delay, further optimization is needed for sure.

+3 -2

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