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XiangShan OpenXiangShan Open-source high-performance RISC-V processor

issue openedOpenXiangShan/XiangShan

NutShell processor dead?

Hi, Has the NutShell project by OSCPU been cancelled? Because it shows that the latest commit was on 19 july. Thanks

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zoujr

commit sha 19d573c8354fcbd74ad12a1b44909d890af4ba7b

BPU[WIP]: Fix many IUM bugs

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zoujr

commit sha 15952c90ace36e93f33f6bc723a119b6293fdeaa

BPU[WIP]: Fix many IUM bugs

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LinJiawei

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Support different SRAMs

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LinJiawei

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Merge remote-tracking branch 'origin/non-inclusive' into HEAD

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commit sha 5ddbb9bb7657d1005c53cd440ed12bb39bf3309e

ecc: dir supports detection of ecc error

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ecc: datastorage supports detection of ecc error

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wangkaifan

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ecc: add missing ecc utility

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Jiawei Lin

commit sha e89c77a53e2efc5d35f36f9a0fbb9184f938b6be

Merge pull request #30 from OpenXiangShan/ecc supports ecc detection

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LinJiawei

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commit sha 35620aa8941abeade18c83d556f3a9c356b31f6f

ci: add cache alias test for ci (#1074)

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Yinan Xu

commit sha 085b0af8b5523eff5aa2b176b1f1b4253147ff38

rs: latch jump pc when deq is blocked (#1076) This commit fixes a bug that causes pc to be wrong values when a jump is blocked for issue and a new jump instruction enters reservation station. When the jump for issue is blocked, we should latch its pc value because the entry has been deallocated from rs (and pc no longer exists in the pc mem).

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PR merged OpenXiangShan/XiangShan

rs: latch jump pc when deq is blocked

This commit fixes a bug that causes pc to be wrong values when a jump is blocked for issue and a new jump instruction enters reservation station. When the jump for issue is blocked, we should latch its pc value because the entry has been deallocated from rs (and pc no longer exists in the pc mem).

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pull request commentOpenXiangShan/XiangShan

rs: latch jump pc when deq is blocked

[Generated by IPC robot] commit: 6795c89e50fa86524e840bd2459a73035a9dea81

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
6795c89 2.069 1.508 2.631 1.602 1.454 0.409 1.467 1.266 3.538 2.169 1.702

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commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
7154d65 2.065 1.504 1.602 1.455 0.409 1.482 1.264 3.535 2.174 1.697
1026804 2.036 1.523 2.297 1.525 1.453 0.410 1.478 1.262 3.244 2.173 1.687
9aca92b 2.078 1.515 2.284 1.525 1.453 0.409 1.504 1.262 3.237 2.175 1.662
fddcfe1 2.056 1.511 2.297 1.527 1.454 0.409 1.506 1.258 3.238 2.169 1.681
5ef7374 2.054 1.511 2.284 1.525 1.455 0.410 1.484 1.258 3.243 2.181 1.680
708ceed 2.071 1.505 2.287 1.525 1.448 0.410 1.492 1.258 3.237 2.181 1.666
1d83cee 2.036 1.502 2.284 1.527 1.455 0.409 1.482 1.262 3.247 2.170 1.680
1f0e2dc 2.066 1.514 2.296 1.525 1.455 0.410 1.485 1.263 3.245 2.168 1.662
64a887e 2.059 1.437 2.264 1.091 1.442 0.358 1.496 0.952 3.199 1.974 1.309
86f7b80 2.059 1.425 2.252 1.093 1.443 0.358 1.514 0.959 3.203 1.975 1.324
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LinJiawei

commit sha afccad5ba6351738a1bb4adc50bc114e42e0a9ba

Support different SRAMs

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PR merged OpenXiangShan/HuanCun

supports ecc detection
  • However, how to handle ecc-error signal is still undefined. Assertion is temporary set.
+270 -12

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commit sha 5ddbb9bb7657d1005c53cd440ed12bb39bf3309e

ecc: dir supports detection of ecc error

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wangkaifan

commit sha 11b82e691054edad66c3df076c00ed4587d64aab

ecc: datastorage supports detection of ecc error

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wangkaifan

commit sha 0d7ae5b65072936f6bf7d9db169613e788fa748b

ecc: add missing ecc utility

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Jiawei Lin

commit sha e89c77a53e2efc5d35f36f9a0fbb9184f938b6be

Merge pull request #30 from OpenXiangShan/ecc supports ecc detection

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ci: add cache alias test for ci

[Generated by IPC robot] commit: 6f5d4bfd03cb8dae6014c6c297d746501acff6ee

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
6f5d4bf 2.103 1.510 2.288 1.525 1.453 0.409 1.471 1.261 3.242 2.174 1.695

master branch:

commit coremark gcc gromacs lbm linux mcf microbench milc namd povray xalancbmk
7154d65 2.065 1.525 1.455 0.410 1.482 3.541 2.174 1.695
1026804 2.036 1.523 2.297 1.525 1.453 0.410 1.478 1.262 3.244 2.173 1.687
9aca92b 2.078 1.515 2.284 1.525 1.453 0.409 1.504 1.262 3.237 2.175 1.662
fddcfe1 2.056 1.511 2.297 1.527 1.454 0.409 1.506 1.258 3.238 2.169 1.681
5ef7374 2.054 1.511 2.284 1.525 1.455 0.410 1.484 1.258 3.243 2.181 1.680
708ceed 2.071 1.505 2.287 1.525 1.448 0.410 1.492 1.258 3.237 2.181 1.666
1d83cee 2.036 1.502 2.284 1.527 1.455 0.409 1.482 1.262 3.247 2.170 1.680
1f0e2dc 2.066 1.514 2.296 1.525 1.455 0.410 1.485 1.263 3.245 2.168 1.662
64a887e 2.059 1.437 2.264 1.091 1.442 0.358 1.496 0.952 3.199 1.974 1.309
86f7b80 2.059 1.425 2.252 1.093 1.443 0.358 1.514 0.959 3.203 1.975 1.324
wakafa1

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William Wang

commit sha 334b08db0e78ec20bec391e651882ec4860d9fee

chore: fix merge conflict

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Li Qianruo

commit sha 5ef7374fb84e4770d036ed0eb296cae97d6c5a1a

top: fix debugIntNode on multi-core (#1071) * scripts,ci: fix broken multi-core build * Fix debugIntNode on multi core

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wakafa

commit sha fddcfe1f099fa3cb6e7b6a6ba9b44943a1fde9dc

dcache: support alwaysReleaseData parameter (#1070)

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Yinan Xu

commit sha 9aca92b99bc760501680614d3be4f34b46d9ed2e

misc: code clean up (#1073) * rename Roq to Rob * remove trailing whitespaces * remove unused parameters

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Yinan Xu

commit sha 102680400cf8ef4c2e8800358ab1f0152b15a61d

fix image url in zh-cn readme (#1075)

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Yinan Xu

commit sha 7154d65e61dadbebf64d138841a8804142559e30

configs, core: update some parameters (#1072) * change ROB to 256 entries * change physical register file to 192 entries * re-organize reservation stations, function units and regfile

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William Wang

commit sha 56aefdef8fd5ff7279e1898c35c46a6b93a99c68

Merge remote-tracking branch 'origin/master' into mem-dep-opt

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YikeZhou

commit sha e92092e77b5a9868f8c415bf01cbc59fc5b98765

MEFreeList: use tailPtr instead of tailPtrNext in free reg cnt

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YikeZhou

commit sha 62d2a04b2f32541ef7bfc530b15331f1e1d4af9c

backend, rename: optimize MEFreeList free logic

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Yinan Xu

commit sha c88c3a2ad8d5caddcf38e659cf944c9bb09bb6ad

backend: clean up exception vector usages (#1026) This commit cleans up exception vector usages in backend. Previously the exception vector will go through the pipeline with the uop. However, instructions with exceptions will enter ROB when they are dispatched. Thus, actually we don't need the exception vector when an instruction enters a function unit. * exceptionVec, flushPipe, replayInst are reset when an instruction enters function units. * For execution units that don't have exceptions, we reset their output exception vectors to avoid ROB to record them. * Move replayInst to CtrlSignals.

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YikeZhou

commit sha 0153cd55ca4811a69821e72f146368fb37d56d9a

backend, rename: elimination psrc directly from intRat

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zhanglinjuan

commit sha ef90f6bd721ba5601e13a151dd5734d17643dfb6

MissQueue: fix bug in miss-merge logic (#1028)

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Lemover

commit sha 82d348fb09576bf1d97afca6011d0fe129e2307f

backend.atomic: when addr_valid, just access tlb, ignore data_valid (#1030)

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Lemover

commit sha ecf1a4b8b1cebf8d1a4467bdd174edb09b091b3a

mmu.l2tlb: set l2tlb's l2 to 32 sets and 2 ways (#1033)

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Lemover

commit sha bf08468c900a8bdd3321cdc3a7f6bb358487a8dd

mmu.tlb: ptw resp will refill both ld & st tlb (#1029) nothing changed but add one parameter to control if ldtlb and sttlb are the same now there two similar parameters: outReplace: when this is true, two ldtlb are 'same', two sttlb are 'same' refillBothTlb: when this is true, the four tlb are same(require outReplace to be true) * mmu.tlb: add param refillBothTlb to refill both ld & st tlb * mmu.tlb: set param refillBothTlb to false

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zoujr

commit sha 65fddcf0358a85e75e3881fcfda6be033c239922

FTQ: Fix the bug that carry calculation is wrong when generating FTB_entry

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Yinan Xu

commit sha b6c0697a0c89a5087c0388eb533595b98ab9d8d6

backend,rs: add counters for critical wakeup sources (#1027) This commit adds critical_wakeup_*_* counters to indicate which function units wake up the instructions in RS. Previously we have wait_for_src_* counters but they cannot represent where the critical operand (the last waiting operand) comes from. We need these counters to optimize fast wakeup logic. If some instructions critically depend on some other instructions, we can think of how we can optimize the wakeup process. Furthermore, this commit also adds a specific counter for FMAs that wakeup other FMAs' third operand. This helps us to decide which strategy is used for FMA fast issue.

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zhanglinjuan

commit sha c33a770f183944c43e78ddc9dbdd9cc8bb331d2c

MissQueue: fix perf bug when MissQ merges load miss (#1037)

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Yinan Xu

commit sha 93b61a80fde4fea6fa320f74997823b340d24bff

regfile: manually reset every registers (#1038) This commit adds manual reset for every register in Regfile. Previously the reset is done by add reset values to the registers. However, physically general-purpose register file does not have reset values. Since all the regfile always has the same writeback data, we don't need to explicitly assign reset data.

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rvcoresjw

commit sha 8130d625fe80f23bf8edea675fa9909ac95c219f

modify dma bus width form 256 to 128 bits (#1041) * add top IOs * modify dma bus data width from 256 to 128 bits * add top single to SimTop.scala

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JinYue

commit sha efcb3cd399278481f661d6c225dac2322173e8ea

ICache: fix fencei not connected

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JinYue

commit sha 03c39bde52118aaa378ae3818378d8be7603b1f9

ICache: fix physical tag bug * Using get_phy_tag function instead of get_tag * This bug happens when using VIPT ICache and setting lage set number

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Jay

commit sha cf2809cc68f2be16a7493b8584c8a77c8c5503ee

Merge pull request #1044 from OpenXiangShan/fix-fencei Fix fencei and physical tag bugs in ICache

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YikeZhou

commit sha 23304efd33f189dcabda24b4ce68478f09026109

backend, freelist: opt flush process in MEFreeList 1) bug fix: updateArchRefCounter should be related with pdest, not old_pdest 2) remove complicated logic of headPtr recovery when flushing

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YikeZhou

commit sha 5036675628140f3d0e72ff7be40cde231cf3f653

Merge branch 'master' into me-timing

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zfw

commit sha 5092a2981be3bf139d23da5f6ba9478e83fbf4e6

ci: update RV64GCB workloads (#1047) This PR replaces coremark, microbench, and all perfromence test workloads by corresponding RV64GCB workloads.

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Yinan Xu

commit sha ebb8ebf8de8980aaa030b36655a892812f423b9d

core: add timer counters for important stages (#1045) This commit adds timer counters for some important pipeline stages, including rename, dispatch, dispatch2, select, issue, execute, commit. We add performance counters for different types of instructions to see the latency in different pipeline stages.

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PR opened OpenXiangShan/HuanCun

supports ecc detection
  • However, how to handle ecc-error signal is still undefined. Assertion is temporary set.
+270 -12

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ecc: add missing ecc utility

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ICache: fix meta_write arbiter bug * write_ready is always false and thus arbiter.io.in.ready is optimized

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