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Yehowshua Immanuel BracketMaster yehowshuaimmanuel.com I like filming and working on compilers.

waviousllc/wav-lpddr-hw 48

Wavious DDR (WDDR) Physical interface (PHY) Hardware

BracketMaster/maeri 5

100% FOSS end to end implementation of an ML accelerator complete with compiler.

BracketMaster/homebrew-rtl 4

Homebrew Tap for BluesSpec Verilog, NextPNR, PRJTrellis etc...

C-Elegans/ulx3s_sdram 4

SDRAM experiments on the ULX3S

BracketMaster/nimulatorPPC 1

A POWER9 emulator written in nim.

BracketMaster/build-gcc 0

some scripts to help with building powerpc gcc on Apple Silicon and in general?

BracketMaster/nimRasterizer 0

A humble triangle rasterizer in Nim.

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Yehowshua Immanuel

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it seems waveform dumping is now fully functional

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should change signal data after delta occurs

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test filename change in vcd tester

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support clk tracing in vcd

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vcd now with progressive writes

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readme need endianess in config; don't need core.nim

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cleanup nimulator entry file a bit

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restructure config

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add instruction on building firmware

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add TODO

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all base VCD features now seemingly functional

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vcds now supports init writes

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preliminary support vcd

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preliminary infrastructure for writing VCDs

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make README instructions clearer

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restructuring to avoid nim warnings

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startedNotCamelCase/Pathsy

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issue commentailisp/commonlisp-vscode

Roswell dependency

I'm also curious, how can I install this plugin without roswell?

snunez1

comment created time in 25 days

issue commentnmigen/nmigen

Undriven signal ends up as module port

You're really supposed to provide an explicit port list iirc.

from nmigen import *
from nmigen.back import verilog

class Test(Elaboratable):
    def __init__(self):
        self.val_out = Signal()

    def elaborate(self, platform):
        m = Module()
        int_sig = Signal(8)
        m.d.comb += self.val_out.eq(int_sig)

        return m

if __name__ == "__main__":
    top = Test()
    with open("test.v", "w") as f:
        f.write(verilog.convert(top, ports=[top.val_out]))
/* Generated by Yosys 0.9+3755 (git sha1 442d19f6, clang 12.0.0 -fPIC -Os) */

(* \nmigen.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "nMigen" *)
module top(val_out);
  (* src = "/Users/yehowshuaimmanuel/test.py:10" *)
  wire [7:0] int_sig;
  (* src = "/Users/yehowshuaimmanuel/test.py:6" *)
  output val_out;
  assign int_sig = 8'h00;
  assign val_out = 1'h0;
endmodule
antonblanchard

comment created time in 25 days

issue commentcisco/ChezScheme

Support for Apple Silicon and MacPorts

Excellent. Just let me know.

ghost

comment created time in 25 days

issue commentcisco/ChezScheme

Support for Apple Silicon and MacPorts

I'm sure if someone wants to ship @cfrisz a new M1 mac he'd be happy to work on getting Chez running on it natively. 😄 After that, getting it in to MacPorts and other package managers is handled by people more familiar with them (or has been in the past, anyway)... see, e.g., #82

I'd be happy to provide ssh access for Apple Silicon as well as Power9 Silicon.

ghost

comment created time in a month

issue commentjustinethier/cyclone

No defmacro support

Not a problem, just something I observed.

Also, your macro docs are down: https://justinethier.github.io/cyclone/docs/api/scheme/cyclone/macros

Lastly, the following seems to not work:

; myfile.scm
(define-syntax while
  (syntax-rules ()
    ((_ condition . body)
     (let loop ()
       (cond (condition
	      (begin . body)
	      (loop)))))))

(define x 0)
(expand '(while (< x 3) (set! x (+ x 1)) (display x)) *global-environment* `())

(exit 0)

icyc -s myfile.scm complains Error: Invalid type: expected pair, found : ()

BracketMaster

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startedoracle/graal

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startedoracle/graal

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issue commentjustinethier/cyclone

No defmacro support

It also seems er-macro-transformer is implicitly defined within define-syntax. https://github.com/justinethier/cyclone/blob/7f4f67f612bcccd2d13a75cbe1e3f282e649a26b/scheme/eval.sld#L533

BracketMaster

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