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If you are wondering where the data of this site comes from, please visit https://api.github.com/users/AugustusWillisWang/events. GitMemory does not store any data, but only uses NGINX to cache data for a period of time. The idea behind GitMemory is simply to give users a better reading experience.
William Wang AugustusWillisWang Institute of Computing Technology, CAS Beijing Time to start.

L-F-Z/ADT_Code 8

ADT Sample Code

Lingrui98/scalaTage 2

A scala version of simple TAGE branch predictor

AugustusWillisWang/NutShell 1

RISC-V SoC designed by students in UCAS

AugustusWillisWang/AIFoundmental-server 0

Server design and document for AIFoundmental course 149543.

AugustusWillisWang/AWS-Cboogle 0

SummerSchoolWork-RewriteBoogleWithC

AugustusWillisWang/C-learning 0

C语言课程作业源码

AugustusWillisWang/Chisel3-Improvement-NUS-CS4215 0

Package for Bundle compare and strict width check in Chisel3.

AugustusWillisWang/Computer-Networking-A-Top-Down-Approach-NOTES 0

《计算机网络-自顶向下方法(原书第6版)》编程作业,Wireshark实验文档的翻译和解答。

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William Wang

commit sha 5720ea6be9088863964004881dc0bef8aa14a774

perf new load wait mechanism

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William Wang

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mem: opt block load logic * load blocked by std invalid will wait for that std to issue * load blocked by load violation wait for that sta to issue

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William Wang

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dcache: simplify main pipe writeback_vaddr

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LinJiawei

commit sha 583eaef148f7b68be6899a29ee40780b6bf62b37

emu.cpp: compatibility fix

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William Wang

commit sha db97763015832db67c244c7ad78160df1dd05679

Merge pull request #31 from OpenXiangShan/logger-patch emu.cpp: compatibility fix

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William Wang

commit sha 5c9e564aea547278090ff5f4dbcf1ea72c1df46d

dcache: fix atom unit pipe req vaddr

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William Wang

commit sha 7d7453029bd21182dd6de4af6961dc14bff0d5f4

dcache: do not require probe vaddr != 0

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William Wang

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dcache: opt banked data read timing

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zhanglinjuan

commit sha 94621d7246683fc05a6b8a7e6f612ff8ecf02988

MainPipe: ReleaseData for all replacement even if it's clean

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William Wang

commit sha b044e2d122276108b97d4240034d9ba734916b22

huancun: bump version

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William Wang

commit sha c8749f14d54c3523cb025c1c9ceda9b996fba808

Merge branch 'releasedata-clean' into l1-l2-com

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William Wang

commit sha 81a344a10faf2f323a36067187031657042834b3

dcache: erase block offset bits in release addr

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PR opened OpenXiangShan/HuanCun

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Non-inclusive: fix dir_init_fn
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mem: update block load logic

Now load will be selected as soon as the store it depends on is ready, which is predicted by Store Sets.

+48 -10

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William Wang

commit sha a2cb1e58f77dfad2f1011387746f34a702c0b060

mem: update block load logic Now load will be selected as soon as the store it depends on is ready, which is predicted by Store Sets

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William Wang

commit sha 66afee5931b07cec005d2ab56ce5f69d547e366b

dcache: fix writeback paddr

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William Wang

commit sha f7ecfd7654773f53951315c1bbae0512a95d2c33

dcache: include vaddr in atomic unit req

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William Wang

commit sha f473b45ec28bceba27dc5f87ab8b129701b8d66a

dcache: fix get_tag() function

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dcache: perf 128KB dcache prototype do not merge
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PR opened OpenXiangShan/XiangShan

mem: update block load logic

Now load will be selected as soon as the store it depends on is ready, which is predicted by Store Sets.

+48 -10

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William Wang

commit sha 8057bb3f6f073f302778283f533a50159b549b8f

mem: update block load logic Now load will be selected as soon as the store it depends on is ready, which is predicted by Store Sets

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issue commentOpenXiangShan/XiangShan

关于lfst的问题

是的, 我们目前使用的是一个弱化版本的 Store Set. LFST 的结果目前使用的很保守, 没有实现原始论文中 Store Set 的全部功能.

与原始论文有差异的地方为:

Making each of the stores dependent on the last fetched store within its store set. Each store specifies one dependence and each load specifies one dependence to form an in-order chain resulting in correct program behavior

目前代码中"追踪指令间的顺序并依次执行"的逻辑有待改进, 后面的指令要在前面的指令结束多个周期后才能开始执行. 这样的话, 如果我们遵循原论文中同一 Store Set 内指令定序的要求, 就会带来较大的性能开销.

我们正在更新 Store Set 以及相关机制的实现, 欢迎参与后续讨论!

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William Wang

commit sha 5f235c685292aa0b75d618d3936a19f18065cb3f

misc: remove unused files, bump difftest

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William Wang

commit sha 7822eea61ce3abe046760e327213c3dec7cc3ee6

misc: update ready-to-run nemu

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William Wang

commit sha 88fbccdd7f0549848a3b175892e1fbb76ca73c46

mem: add vaddr forward profiling framework

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William Wang

commit sha 672f1d35be39207dcee2737156eaf93540f3f3e4

mem: use vaddr match, paddr fix forward in SQ Vaddr Match, Paddr Fix (VMPF) store to load forward uses vaddr cam result to select data to be forwarded. Vaddr cam result and paddr cam result will be compared to check if vaddr based forward is correct. If not, an microarichitectural exception should be raised to flush SQ and committed sbuffer. TODO: forward fail microarichitectural exception

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William Wang

commit sha 41962d72a68d0f592d81244f96d9f01708ea990a

mem: use vaddr match, paddr fix forward in sbuffer Now we use vaddr tag to select data to be forwarded in sbuffer. Vtag / ptag match result will be compared latter to check if vaddr based forward is correct. If not, an microarichitectural exception should be raised to flush SQ and committed sbuffer. TODO: forward fail microarichitectural exception

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William Wang

commit sha 112138964481e46a325f56dbeb87ccce43efc1ac

mem: drain sbuffer when v/ptag mismatch

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William Wang

commit sha 4f2594f26d88fd26a6bac6d9282b9688841d753c

sbuffer: ignore invalid forward request

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William Wang

commit sha 6e162816a7fb0411a2efd943c730c1895f3f2645

mem: enable vaddr based sbuffer forward Frontend will be refactored soon. Rollback will not be added until that

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William Wang

commit sha 6a2edd8a8b39d7320fa1ccd85015de85dec8f3f3

rob: support replay inst from rob

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William Wang

commit sha 4457bfcd222457b14716df63abe6eb389c4941d7

mem: replay forward_fail inst from rob

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William Wang

commit sha 0a24fac31eaa52dc7a19bf1f294df4cda9bf1624

Merge remote-tracking branch 'origin/master' into vaddr-fwd

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William Wang

commit sha 4887ca7fbd391a890b1877f9399c80b25572a67d

mem: fix replay inst from rob logic

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William Wang

commit sha 3db2cf7579cc9b3c36124096d12f797410f73430

mem: loadpipe will not miss if fullForward succeed New option `EnableFastForward` is added to config list. EnableFastForward will reduce L1D$ miss but make timing worse. * `forwardMaskFast` is generated at load_s1, it is used to generate fastUop for fast wakeup * `forwardMask` is generated at load_s2, it will be used to check if forward result is correct

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William Wang

commit sha ce28536f0fddf6bfda31615ff3dd5e01e2a3c0e9

mem: fix rsFeedback for fast forward

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William Wang

commit sha e3f759ae573d6f4fabbfe9e4dcf7987b1d32d06d

mem: add load to load addr fastpath framework

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William Wang

commit sha 00a565697570aee160a003c022b96a96ff0850b7

mem: mark inst as datavalid in lq if fullForward

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William Wang

commit sha 65c67692a78bb17d1b417d2a4988cbd99eb6a4c0

mem: opt sbuffer_state update timing * Delay need_uarch_drain for one cycle

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William Wang

commit sha 103b691438e3afd99c245eed144b9149ff7c61ef

mem: reduce refill writeback delay by 1 cycle * Now inst being refilled currently can be selected as wb candidate

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William Wang

commit sha 594ba8ac93360d08b5da8cc83597e39f211db3fe

mem: let lq refill width be equal to l1d bus width

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William Wang

commit sha 7ab59370ffc775aed60862417b6a48af7db40b5f

chore: update load_miss_penalty_to_use counter

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William Wang

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dcache: reduce banked data load conflict

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William Wang

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dcache: reduce banked data load conflict

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